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brook t ree brooktree division ?rockwell semiconductor systems, inc. ? 9868 scranton road ? san diego, ca 92121-3707 619-452-7580 ?1-800-2-bt-apps ? fax: 619-452-1249 ? internet: apps@brooktree.com ? l848a_a distinguishing features fully pci rev. 2.1 compliant auxiliary gpio data port and video data port supports image resolutions up to 768x576 (full pal resolution) supports complex clipping of video source zero wait state pci burst writes field/frame masking support to throttle bandwidth to target multiple ycrcb and rgb pixel formats supported on output supports ntsc/secam/pal analog input image size scalable down to icon using vertical & horizontal interpolation ?tering multiple composite and s-video inputs supports different destinations for even and odd ?lds supports different color space/scaling factors for even and odd ?lds support for mapping of video to 225 color palette vbi data capture for closed captioning, teletext and intercast data decoding additional features in bt848a/849a only supports peaking requires only one crystal digital camera support through gpio port support for wst decode (bt849a only) applications pc tv intercast receiver desktop video phone motion video capture still frame capture teletext/intertext vbi data services capture bt848 is a complete, low cost single-chip solution for analog ntsc/pal/secam video capture on the pci bus. as a bus master, bt848 does not require any local memory buffers to store video pixel data which signi? cantly minimizes the hardware cost for this architecture. bt848 takes advantage of the pci-based systems high bandwidth and inherent multimedia capability. it is designed to be interoperable with any other pci multimedia device at the component or board level, thus enabling video capture and overlay capability to be added to pci systems in a modular fashion at low cost. the bt848 solution is independent of the pci system bus topology and may be used in a variety of sys- tem bus organizations: directly on a motherboard planar bus, on a card for a pla- nar or secondary bus. the bt848a/849a are fully backward compatible enhancements to the bt848. the bt848a and 849a both include all the functionality of the bt848, while adding support for peaking, single crystal operation, and digital camera support. functional block diagram advance information this document contains information on a product under development. the parametric information contains target parameters that are subject to change. analog mux agc 40 mhz adc 40 mhz adc decimation lpf ultralock and clock generation video timing unit iic jtag pixel format conversion 630 byte fifo digital camera target initiator pci i/f muxin muxout syncdet refout yin cin xtal luma-chroma separation and chroma demod single-chip video capture for pci bt848/848a/849a input (bt848a/849a) horizontal, vertical and temporal scaling dma controller and gpio port
copyright ?1997 brooktree corporation. all rights reserved. print date: february 1997 brooktree reserves the right to make changes to its products or speci?ations to improve performance, reliability, or manufacturability. information furnished by brooktree corporation is believed to be accurate and reliable. however, no responsibility is assumed by brooktree corporation for its use; nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by its implication or otherwise under any patent or patent rights of brooktree corporation. brooktree products are not designed or intended for use in life support appliances, devices, or systems where malfunction of a brooktree product can reasonably be expected to result in personal injury or death. brooktree customers using or selling brooktree products for use in such applications do so at their own risk and agree to fully indemnify brooktree for any damages resulting from such improper use or sale. brooktree is a registered trademark of brooktree corporation. product names or services listed in this publication are for identi?ation purposes only, and may be trademarks or registered trademarks of their respective companies. all other marks mentioned herein are the property of their respective holders. speci?ations are subject to change without notice. printed in the united states of america model number package ambient temperature range bt848kpf 160-pin pqfp 0?c to +70?c bt848akpf 160-pin pqfp 0?c to +70?c BT849AKPF 160-pin pqfp 0?c to +70?c ordering information
brook t ree iii l848a_a t able of c ontents list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 video capture over pci bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 supports intel intercast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 bt848a analog video and digital camera capture over the pci bus . . . . . . . . . . . . 2 dma channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 pci bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ultralock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 scaling and cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 input interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 gpio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 vertical blanking interval data capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ultralock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 the challenge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 operation principles of ultralock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 composite video input formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 y/c separation and chroma demodulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 video scaling, cropping, and temporal decimation . . . . . . . . . . . . . . . . . . . . . . . . . . 21 horizontal and vertical scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 luminance scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 peaking (bt848a and bt849a only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 chrominance scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 scaling registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 image cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 cropping registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 temporal decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
brook t ree iv l848a_a bt848/848a/849a single-chip video capture for pci t able of c ontents video adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 the hue adjust register (hue) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 the contrast adjust register (contrast). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 the saturation adjust registers (sat_u, sat_v) . . . . . . . . . . . . . . . . . . . . . . . . . . 33 the brightness register (bright). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 automatic chrominance gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 low color detection and removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 coring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 vbi data output interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 video data format conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 pixel data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 video control code status data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 ycrcb to rgb conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 gamma correction removal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 ycrcb sub-sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 byte swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 video and control data fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 logical organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 fifo data interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 physical implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 fifo input/output rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 target memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 risc program setup and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 risc instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 complex clipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 executing instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 fifo over-run conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 fifo data stream resynchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 electrical interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 analog signal selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 multiplexer considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 autodetection of ntsc or pal/secam video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 flash a/d converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 a/d clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 power-up operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 automatic gain controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 crystal inputs and clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 single crystal operation (bt848a/849a only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2x oversampling and input filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
brook t ree v l848a_a t able of c ontents bt848/848a/849a single-chip video capture for pci pci bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 general purpose i/o port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 gpio normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 gpio spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 digital video in support (bt848a/849a only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 need for functional veri?ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 jtag approach to testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 optional device id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 veri?ation with the tap controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 pc board layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 ground planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 power planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 digital signal interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 analog signal interconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 latch-up avoidance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 control register de?itions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 pci con?uration space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 pci con?uration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 vendor and device id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 command and status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 revision id and class code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 latency timer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 base address 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 interrupt line, interrupt pin, min_gnt, max_lat register . . . . . . . . . . . . . . . . . . . . . . 89 local registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 device status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 input format register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 temporal decimation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 msb cropping register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 vertical delay register, lower byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 vertical active register, lower byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 horizontal delay register, lower byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 horizontal active register, lower byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 horizontal scaling register, upper byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
brook t ree vi l848a_a bt848/848a/849a single-chip video capture for pci t able of c ontents horizontal scaling register, lower byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 brightness control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 miscellaneous control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 luma gain register, lower byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 chroma (u) gain register, lower byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 chroma (v) gain register, lower byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 hue control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 sc loop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 output format register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 vertical scaling register, upper byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 vertical scaling register, lower byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 test control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 agc delay register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 burst delay register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 adc interface register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 video timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 software reset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 color format register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 color control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 capture control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 vbi packet size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 vbi packet size / delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 pll reference multiplier - pll_f_lo (bt848a/849a only) . . . . . . . . . . . . . . . . . . . . 111 pll reference multiplier - pll_f_hi (bt848a/849a only) . . . . . . . . . . . . . . . . . . . . . 111 integer- pll-xci (bt848a/849a only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 field capture counter-(fcap) (bt848a/849a only) . . . . . . . . . . . . . . . . . . . . . . . . . . 111 interrupt status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 interrupt mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 risc program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 risc program start address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 gpio and dma control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 gpio output enable control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 gpio registered input control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 gpio data i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 i 2 c data/control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
brook t ree vii l848a_a t able of c ontents bt848/848a/849a single-chip video capture for pci control register digital video in support (bt848a/849a only) . . . . . . . . . . . . . . . 119 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 digital video signal interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 timing generator load byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 timing generator control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 luma gain register, lower byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 chroma (v) gain register, lower byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 chroma (u) gain register, lower byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 hdelay/hscale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 parametricinformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 dc electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 ac electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 datasheet revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
brook t ree viii l848a_a bt848/848a/849a single-chip video capture for pci l ist o f f igures list of figures figure 1. bt848/848a/849a detailed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 2. bt848 video decoder and scaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. bt848/848a/849a pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 4. ultralock behavior for ntsc square pixel output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 5. y/c separation and chroma demodulation for composite video . . . . . . . . . . . . . . . . . . 19 figure 6. y/c separation filter responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 7. filtering and scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 8. optional horizontal luma low-pass filter responses. . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 9. combined luma notch, 2x oversampling and optional low-pass filter response (ntsc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 10. combined luma notch, 2x oversampling and optional low-pass filter response (pal/secam) . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 11. frequency responses for the four optional vertical luma low-pass filters . . . . . . . . . 23 figure 12. combined luma notch and 2x oversampling filter response . . . . . . . . . . . . . . . . . . . . 23 figure 13. peaking filters (bt848a/849a only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 14. luma peaking filters with 2x oversampling filter and luma notch (bt848a/849a only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 15. effect of the cropping and active registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 16. regions of the video signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 17. coring map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 18. regions of the video frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 19. vbi timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 20. vbi section block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 21. video data format converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 22. data fifo block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 23. risc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 24. example of bt848 performing complex clipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 25. typical external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 26. clock options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 27. luma and chroma 2x oversampling filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 28. pci block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 29. gpio normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 30. gpio spi input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 31. gpio spi output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 32. video timing in spi mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 33. basic timing relationships for spi mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 34. ccir 656 or bytestream interface to digital input port . . . . . . . . . . . . . . . . . . . . . . . . . . 73
brook t ree ix l848a_a l ist o f f igures bt848/848a/849a single-chip video capture for pci figure 35. the relationship between scl and sda. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 36. i 2 c typical protocol diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 37. instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 38. example ground plane layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 39. optional regulator circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 40. typical power and ground connection diagram and parts list . . . . . . . . . . . . . . . . . . . 82 figure 41. pci con?uration space header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 42. clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 43. gpio timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 44. jtag timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 45. 160-pin pqfp package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
brook t ree x l848a_a bt848/848a/849a single-chip video capture for pci l ist of t ables list of tables table 1. pci video decoder product family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 table 2. pin descriptions grouped by pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. bt848 pin list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. video input formats supported by the bt848 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5. register values for video input formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 6. scaling ratios for popular formats using frequency values . . . . . . . . . . . . . . . . . . . . . . 28 table 7. color formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 8. byte swapping map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 9. status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 10. table of pci bus access latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 11. risc instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 12. fifo full/almost full counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 13. synchronous pixel interface (spi) gpio signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 14. pin de?ition of gpio port when using digital video-in mode . . . . . . . . . . . . . . . . . . . . 73 table 15. device identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 16. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 17. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 18. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 19. clock timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 20. gpio spi mode timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 21. power supply current parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 22. power supply current parameters (bt848a/849a only) . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 23. jtag timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 24. decoder performance parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 25. bt848 datasheet revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
brook t ree 1 l848a_a f unctional d escription functional overview video capture over pci bus the bt848/848a/849a integrates an ntsc/pal/secam composite & s-video decoder, scaler, dma controller, and pci bus master on a single device. bt848/848a/849a can place video data directly into host memory for video cap- ture applications and into a target video display frame buffer for video overlay ap- plications. as a pci initiator, bt848/848a/849a can take control of the pci bus as soon as it is available, thereby avoiding the need for on-board frame buffers. bt848/848a/849a contains a pixel data fifo to decouple the high speed pci bus from the continuous video data stream. figure 1 shows a block diagram of the bt848/848a/849a, and figure 2 shows a detailed block diagram of the decoder and scaler sections. the video data input may be scaled, color translated, and burst transferred to a target location on a ?ld basis. this allows for simultaneous preview of one ?ld and capture of the other ?ld. alternatively, bt848/848a/849a is able to capture both ?lds simultaneously or preview both ?lds simultaneously. the ?lds may be interlaced into memory or sent to separate ?ld buffers. the bt849a includes all the capability in the bt848a and adds support for wst decoding (the encoding method for european based teletext). the bt849a imple- ments a signi?ant amount of wst decoding in s/w ensuring a very low cost tv card for use in locations requiring teletext see table 1 for a comparison of the bt848/848a/849a. supports intel intercast the bt848/848a/849a fully supports the intel intercast technology. intel intercast technology combines the rich programming of television and the exciting world of the internet on your pc. imagine watching a news broadcast and simultaneously getting a web page providing a historical perspective. or viewing a music video and ordering tickets on the internet for the bands next appearance in your area. or enjoying a favorite show and getting special web pages associated with that program. now your pc can let you interact with television in all kinds of new and exciting ways.
bt848/848a/849a single-chip video capture for pci brook t ree 2 f unctional d escription functional overview l848a_a bt848a analog video and digital camera capture over the pci bus the bt848a provides support for digital cameras. the bt848a includes a digital camera port providing the ability to perform digital capture when a bt848a is used in the development of a video board product. the bt848a is fully compatible with the bt848. the datasheet de?es the registers and functionality required for imple- menting analog video capture support. in order to implement digital video inter- face, refer to the digital video section of the datasheet. note the majority of the register settings are identical for both analog and digital video support. the digital video section identi?s all changes, additional registers, all changes to the analog register setting that are required in order to support digital video. the bt848a can accept digital video from a multitude of sources including the silicon vision and logitech video cameras. the digital stream is routed to the high quality down scaler and color adjustment processing. it is then bus mastered into system memory or displayed via the graphics frame buffer. dma channels bt848/848a/849a provides two dma channels for the odd and even ?lds, each controlled by a pixel instruction list. this instruction list is created by the bt848 device driver and placed in the host memory. the instructions control the transfer of pixels to target memory locations on a byte resolution basis. complex clipping can be accomplished by the instruction list, blocking the generation of pci bus cy- cles for pixels that are not to be seen on the display. the dma channels can be programmed on a ?ld basis to deliver the video data in packed or planar format. in packed mode, ycrcb data is stored in a single con- tinuous block of memory. in planar mode, the ycrcb data is separated into three streams which are burst to different target memory blocks. having the video data in planar format is useful for applications where the data compression is accom- plished via software and the cpu. table 1. pci video decoder product family bt848 bt848a bt849a composite, s-video multi-standard video decoder and pci bus master xxx peaking, single crystal operation, digital camera support xx wst (teletext) decoding support x
brook t ree 3 f unctional d escription functional overview l848a_a bt848/848a/849a single-chip video capture for pci figure 1. bt848/848a/849a detailed block diagram video decoder video scaler ycrcb 4:2:2, 4:1:1 csc/gamma 8-bit dither format mux fifos y: 70x36 cb: 35x36 cr: 35x36 # dwords dma controller pci initiator instruction queue address generator fifo data mux gpio i 2 c master pci con? registers pci target controller interrupts ad mux parity generator analog video pci bus pci bus video data format converter local registers wr instr data rd (digital video input bt848a & bt849a only) gpio
bt848/848a/849a single-chip video capture for pci brook t ree 4 f unctional d escription functional overview l848a_a pci bus interface bt848/848a/849a is designed to ef?iently utilize the available 132 mb/s pci bus. the 32-bit dwords are output on the pci bus with the appropriate image data under the control of the dma channels. the video stream consumes bus bandwidth with average data rates varying from 44 mb/s for full size 768x576 pal rgb32, to 4.6 mb/s for ntsc cif 320 x 240 rgb16, to 0.14 mb/s for ntsc icon 80 x 60 8-bit mode. the pixel instruction stream for the dma channels consumes a minimum of 0.1 mb/s. achieving high performance throughput on pci may be a problem with slow targets and long bus access latencies. the bt848/848a/849a provides the means for handling the bandwidth bottlenecks that sometimes occur depending on a particular system con?uration. bt848/848a/849as ability to gracefully de- grade and to recover from fifo overruns to the nearest pixel in real-time is the best possible solution to these system bottlenecks. figure 2. bt848 video decoder and scaler block diagram notes: (1). bt848 only. (2). bt848a and bt849a only. muxout mux0 mux1 xt1o xt1i xt0o xt0i syncdet (!) agccap refout yref yin yref+ cref cin cref+ clevel c a/d y a/d oversampling low-pass filter y/c separation chroma demod hue, saturation, and brightness adjust horizontal and vertical filtering and scaling clocking mux2 agc and sync detect to fifo input data formatter mux3 (2)
brook t ree 5 f unctional d escription functional overview l848a_a bt848/848a/849a single-chip video capture for pci ultralock the bt848/848a/849a employs a proprietary technique known as ultralock to lock to the incoming analog video signal. it will always generate the required num- ber of pixels per line from an analog source in which the line length can vary by as much as a few microseconds. ultralocks digital locking circuitry enables the vid- eostream decoders to quickly and accurately lock on to video signals, regardless of their source. since the technique is completely digital, ultralock can recognize unstable signals caused by vcr headswitches or any other deviation, and adapt the locking mechanism to accommodate the source. ultralock uses nonlinear tech- niques which are dif?ult, if not impossible, to implement in genlock systems. and unlike linear techniques, it adapts the locking mechanism automatically. scaling and cropping the bt848/848a/849a can reduce the video image size in both horizontal and ver- tical directions independently using arbitrarily selected scaling ratios. the x and y dimensions can be scaled down to one-sixteenth of the full resolution. horizontal scaling is implemented with a six-tap interpolation ?ter while up to 5-tap interpo- lation is used for vertical scaling with a line store. the video image can be arbitrarily cropped by reducing the number of active scan lines and active horizontal pixels per line. the bt848/848a/849a supports a temporal decimation feature that reduces video bandwidth by allowing frames or ?lds to be dropped from a video sequence at ?ed but arbitrarily selected intervals. input interface analog video signals are input to the bt848/848a/849a via a three-input multi- plexer that can select between three composite source inputs or between two com- posite and a single s-video input source. when an s-video source is input to the bt848/848a/849a, the luma component is fed through the input analog multiplex- er, and the chroma component is fed directly into the c input pin. an automatic gain control circuit enables the bt848 to compensate for non-standard amplitudes in the analog signal input. on the bt848a and bt849a there is an additional mux input (providing a four-input multiplexer). the clock signal interface consists of two pairs of pins for crystal connection and two clock output pins. one pair of crystal pins is for connection to a 28.64 mhz (8*ntsc fsc) crystal which is selected for ntsc operation. the other is for pal operation with a 35.47 mhz (8*pal fsc) crystal. either fundamental or third harmonic crystals may be used. alternatively, cmos oscillators may be used. gpio the bt848/848a/849a provides a 24-bit general purpose i/o bus. this interface can be used to input or output up to 24 general purpose i/o signals. alternatively, the gpio port can be used as a means to input or output video decoder data. for ex- ample, the bt848/848a/849a can input the video data from an external video de- coder and bypass the bt848/848a/849as internal video decoder block. another application is to output the video decoder data from the bt848/848a/849a over the gpio bus for use by external circuitry.
bt848/848a/849a single-chip video capture for pci brook t ree 6 f unctional d escription functional overview l848a_a vertical blanking interval data capture bt848/848a/849a provides a complete solution for capturing and decoding verti- cal blanking interval (vbi) data. the bt848/848a/849a can operate in a vbi line output mode, in which the vbi data is only captured during select lines. this mode of operation enables concurrent capture of vbi lines containing ancillary data and normal video image data. in addition, the bt848/848a/849a supports a vbi frame output mode, in which every line in the video frame is treated as if it was a vbi line. this mode of operation is designed for use with still frame capture/processing applications. i 2 c interface the bt848/848a/849a provides a two-wire inter-integrated circuit (i 2 c) inter- face. as an i 2 c master, bt848/848a/849a can program other devices on the video card, such as a tv tuner. serial clock and data lines, scl and sda are used to transfer data at a rate of 100 kbits/s.
brook t ree 7 f unctional d escription pin descriptions l848a_a bt848/848a/849a single-chip video capture for pci pin descriptions table 2 provides a description of pin functions, grouped by common function, table 3 is a list of pin names in pin-number order, and figure 3 shows the pinout diagram. note: pins with alternate de?itions on the bt848a and bt849a are indicated by shading table 2. pin descriptions grouped by pin function (1 of 6) pin # pin name i/o signal description pci interface (50 pins) 11 clk i clock this input provides timing for all pci transactions. all pci sig- nals except rst and int a are sampled on the rising edge of clk, and all other timing parameters are de?ed with respect to this edge. the bt848 supports a pci clock of up to 33.333333 mhz. 9 rst i reset this input three-states all pci signals asynchronous to the clk signal. 13 gnt i grant agent granted bus. 28 idsel i initialization device select this input is used to select the bt848 during con?uration read and write transactions. 15?7, 20?4, 29?2, 35?8, 53?5, 58?2, 66?9, 72?5 ad[31:0] i/o address/data these three-state, bi-directional, i/o pins transfer both address and data information. a bus transaction consists of an address phase followed by one or more data phases for either read or write operations. the address phase is the clock cycle in which frame is ?st asserted. during the address phase, ad[31:0] contains a byte address for i/o operations and a dword address for con?uration and memory operations. during data phases, ad[7:0] contains the least signi?ant byte and ad[31:24] con- tains the most signi?ant byte. read data is stable and valid when trd y is asserted and write data is stable and valid when ird y is asserted. data is transferred during the clocks when both trd y and ird y are asserted. 27, 39, 52, 65 cbe [3:0] i/o bus com- mand/byte enables these three-state, bi-directional, i/o pins transfer both bus command and byte enable information. during the address phase of a transaction, cbe [3:0] contain the bus command. during the data phase, cbe [3:0] are used as byte enables. the byte enables are valid for the entire data phase and determine which byte lanes carry meaningful data. cbe [3] refers to the most signi?ant byte and cbe [0] refers to the least signi?ant byte.
bt848/848a/849a single-chip video capture for pci brook t ree 8 f unctional d escription pin descriptions l848a_a 51 par i/o parity this three-state, bi-directional, i/o pin provides even parity across ad[31:0] and cbe [3:0]. this means that the number of 1s on par, ad[31:0], and cbe [3:0] equals an even num- ber. par is stable and valid one clock after the address phase. for data phases, par is stable and valid one clock after either trd y is asserted on a read or ird y is asserted on a write. once valid, par remains valid until one clock after the completion of the current data phase. par and ad[31:0] have the same timing, but par is delayed by one clock. the target drives par for read data phases; the master drives par for address and write data phases. 42 frame i/o cycle frame this sustained three-state signal is driven by the current master to indicate the beginning and duration of an access. frame is asserted to signal the beginning of a bus transac- tion. data transfer continues throughout assertion. at deas- sertion, the transaction is in the ?al data phase. 43 irdy i/o initiator ready this sustained three-state signal indicates the bus masters readiness to complete the current data phase. ird y is used in conjunction with trd y . when both ird y and trd y are asserted, a data phase is completed on that clock. during a read, ird y indicates when the initiator is ready to accept data. during a write, ird y indicates when the initiator has placed valid data on ad[31:0]. wait cycles are inserted until both ird y and trd y are asserted together. 44 trdy i/o target ready this sustained three-state signal indicates the targets readi- ness to complete the current data phase. ird y is used in conjunction with trd y . when both ird y and trd y are asserted, a data phase is completed on that clock. during a read, trd y indicates when the target is pre- senting data. during a write, trd y indicates when the target is ready to accept the data. wait cycles are inserted until both ird y and trd y are asserted together. 45 devsel i/o device select this sustained three-state signal indicates device selection. when actively driven, devsel indicates the driving device has decoded its address as the target of the current access. 46 stop i/o stop this sustained three-state signal indicates the target is requesting the master to stop the current transaction. 49 perr i/o parity error report data parity error. 14 req o request agent desires bus. 8 inta o interrupt a this signal is an open drain interrupt output. 50 serr o system error report address parity error. open drain. see pci speci?ation 2.1 for further documentation table 2. pin descriptions grouped by pin function (2 of 6) pin # pin name i/o signal description
brook t ree 9 f unctional d escription pin descriptions l848a_a bt848/848a/849a single-chip video capture for pci general purpose i/o (27 pins) 82?9, 92?9, 110?17 gpio[23:0] i/o general purpose i/o 24 bits of programmable i/o. these pins are internally pulled up to vddg. gpio[23] gpio[22] gpio[21] gpio[20] gpio[19] gpio[18] gpio[17] gpio[16] gpio[9] gpio[8] gpio[7:0] o o o o o o o o i i i clkx1 field vactive vsync hactive hsync composite active composite sync vsync/field hsync video data input at gpclk = clkx2 rate bt848a and bt849a pin decoding when in digital video input and spi mode. 119 gpintr i gp interrupt gp port requests an interrupt. internally pulled up to vddg. 118 gpwe i gp write enable gp port write enable for registered inputs. internally pulled up to vddg. 108 gpclk i/o gp clock video clock. internally pulled up to vddg. input stage (14 pins) 141 mux0 i analog composite video inputs to the on-chip input multi- plexer. used to select between three composite sources or two composite and one s-video source. unused pins should be connected to ground. 143 mux1 i 145 mux2 i 139 muxout o the analog video output of the 3 to 1 multiplexer. must con- nect to the yin pin. 138 yin i the analog composite or luma input to they-adc. 154 cin i the analog chroma input to the c-adc. 147 syncdet i the sync stripper input used to generate timing information for the agc circuit. must be connected through a 0.1 m f capacitor to the same source as the y-adc. a 1 m w bleeder resistor should be connected to ground. mux3 i in the bt848a and bt849a the syncdet is not required and is used as a fourth mux input. analog composite video inputs to the on-chip input multi- plexer. used to select between three composite sources or two composite and one s-video source. unused pins should be connected to ground. 131 agccap a the agc time constant control capacitor node. must be con- nected to a 0.1 m f capacitor to ground. table 2. pin descriptions grouped by pin function (3 of 6) pin # pin name i/o signal description
bt848/848a/849a single-chip video capture for pci brook t ree 10 f unctional d escription pin descriptions l848a_a 133 refout o output of the agc which drives the yref+ and cref+ pins. refout o in the bt848aand bt849a, the external 30 k, 30 k, and 2 k resistors are not required. however, the 0.1 m f capacitor ground to gnd is still needed (see figure 25). 137 yref+ i the top of the reference ladder of the y-adc. this should be connected to refout. 150 yref i the bottom of the reference ladder of the y-adc. this should be connected to analog ground (agnd). 151 cref+ i the top of the reference ladder of the c-adc. this should be connected to refout. 157 cref i the bottom of the reference ladder of the c-adc. this should be connected to analog ground (agnd). 158 clevel i an input to provide the dc level reference for the c-adc. this voltage should be one half of cref+. clevel i in the bt848a and bt849a, this input is internally generated. no external components are required. i 2 c interface (2 pins) 78 scl i/o serial clock bus clock, output open drain. 79 sda i/o serial data bit data or acknowledge, output open drain. video timing clock interface (5 pins) 102 xt0i a clock zero pins. a 28.636363 mhz (8*fsc) fundamental (or third harmonic) crystal can be tied directly to these pins, or a single-ended oscillator can be connected to xt0i. cmos level inputs must be used. this clock source is selected for ntsc input sources. when the chip is con?ured to decode pal but not ntsc (and therefore only one clock source is needed), the 35.468950 mhz source is connected to this port (xt0). 103 xt0o a xt0i a in the bt848a and bt849a, this is the only clock source required to decode all video formats. if only one source is used the frequency must be 28.636363 mhz (50 ppm) and a series resistor must be added to the layout. alternatively, the bt848a and bt849a may be con?ured exactly as the bt848 (using 28.636363 and 35.468950 mhz sources). xt0o a 105 xt1i a clock one pins. a 35.468950 mhz (8*fsc) fundamental (or third harmonic) crystal can be tied directly to these pins, or a single-ended oscillator can be connected to xt1i. cmos level inputs must be used. this clock source is selected for pal input sources. if either ntsc or pal is being decoded, and therefore only xt0i and xt0o are connected to a crystal, xt1i should be tied either high or low, and xt1o must be left ?ating. 106 xt1o a table 2. pin descriptions grouped by pin function (4 of 6) pin # pin name i/o signal description
brook t ree 11 f unctional d escription pin descriptions l848a_a bt848/848a/849a single-chip video capture for pci 104 numxtal i crystal format pin. this pin is set to indicate whether one or two crystals are present so that the bt848 can select xt1 or xt0 as the default in auto format mode. a logical zero on this pin indicates one crystal is present. a logical one indicates two crystals are present. this pin is internally pulled up to vddg. jtag (5 pins) 3 tck i test clock. used to synchronize all jtag test structures. when jtag operations are not being performed, this pin must be driven to a logical low. 5 tms i test mode select. jtag input pin whose transitions drive the jtag state machine through its sequences. when jtag operations are not being performed, this pin must be left ?at- ing or tied high. 7 tdi i test data input. jtag pin used for loading instructions to the tap controller or for loading test vector data for bound- ary-scan operation. when jtag operations are not being performed, this pin must be left ?ating or tied high. 6 tdo o test data output. jtag pin used for verifying test results of all jtag sampling operations. this output pin is active for certain jtag operations and will be three-stated at all other times. 2 trst i test reset. jtag pin used to initialize the jtag controller. this pin is tied low for normal device operation. when pulled high, the jtag controller is ready for device testing. note: not all pcs drive the pci bus trst pin. in these computers, if the trst pin on the bt848 board is connected to trst on the pci bus (which is not driven) the bt848 may power up in an unde?ed state. in these designs, the trst pin on the bt848 card must be tied low (disabling jtag). power & ground (57 pins) 1, 18, 40, 63, 81, 101, 120 vdd +5v p power supply for digital circuitry. all vdd pins must be con- nected together as close to the device as possible. a 0.1 m f capacitor should be connected between each group of vdd pins and the ground plane as close to the device as possible. 130, 134, 136, 148, 152, 156 vaa +5v vpos +5v p power supply for analog circuitry. all vaa pins and vpos must be connected together as close to the device as possi- ble. a 0.1 m f ceramic capacitor should be connected between each group of vaa pins and the ground plane as close to the device as possible. 10, 25, 33, 47, 56, 70, 76 vddp pci vio p power supply for pci bus signals. a 0.1 m f ceramic capacitor should be connected between the vddp pins and the ground plane as close to the device as possible. table 2. pin descriptions grouped by pin function (5 of 6) pin # pin name i/o signal description
bt848/848a/849a single-chip video capture for pci brook t ree 12 f unctional d escription pin descriptions l848a_a 90, 109, 123 vddg +5v p power supply for gpio port signals. a 0.1 m f ceramic capac- itor should be connected between the vddg pins and the ground plane as close to the device as possible. 12, 19, 26, 34, 41, 48, 57, 64, 71, 77, 80, 91, 100, 107, 121, 122, 160 gnd g ground for digital circuitry. all gnd pins must be connected together as close to the device as possible. 132, 135, 140, 142, 144, 146, 149, 153, 155, 159 agnd, vneg g ground for analog circuitry. all agnd pins and vneg must be connected together as close to the device as possible. 4 pvref a this pin should be connected to gnd (this reference signal may be connected to the +3.3 v pin on the pci bus, even if the pci bus does not supply 3.3 v). 124?29 n/c no connect reserved gpx[5:0] i/o remapped from gpio [5:0] these pins are remapped on the bt848a and bt849a to pro- vide the same functionality as on the bt848 but on a different pin. i/o column legend: i = digital input o = digital output i/o = digital bidirectional a = analog g = ground p = power table 2. pin descriptions grouped by pin function (6 of 6) pin # pin name i/o signal description
brook t ree 13 f unctional d escription pin assignments l848a_a bt848/848a/849a single-chip video capture for pci pin assignments figure 3. bt848/848a/849a pinout diagram note: bt848a and bt849a pin alternate definitions indicated in (). 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 vdd trst tck pvref tms tdo tdi int a rst vddp clk gnd gnt req ad[31] ad[30] ad[29] vdd gnd ad[28] ad[27] ad[26] ad[25] ad[24] vddp gnd cbe [3] idsel ad[23] ad[22] ad[21] ad[20] vddp gnd ad[19] ad[18] ad[17] ad[16] cbe [2] vdd gnd agnd clevel cref vaa agnd cin agnd vaa cref+ yref agnd vaa syncdet (mux3) agnd mux2 agnd mux1 agnd mux0 agnd muxout yin yref+ vaa agnd vaa refout vneg agccap vpos n/c (gpx0) n/c (gpx1) n/c (gpx2) n/c (gpx3) n/c (gpx4) n/c (gpx5) vddg gnd gnd gnd frame ird y trd y devsel st op vddp gnd perr serr pa r cbe [1] ad[15] ad[14] ad[13] vddp gnd ad[12] ad[11] ad[10] ad[9] ad[8] vdd gnd cbe [0] ad[7] ad[6] ad[5] ad[4] vddp gnd ad[3] ad[2] ad[1] ad[0] vddp gnd scl sda gnd vdd gpintr gpwe gpio[0] gpio[1] gpio[2] gpio[3] gpio[4] gpio[5] gpio[6] gpio[7] vddg gpclk gnd xt1o xt1i vdd gnd gpio[8] (hsync) gpio[9] (vsync/field) gpio[10] gpio[11] gpio[12] gpio[13] gpio[14] gpio[15] gnd vddg gpio[16] (composite sync) gpio[17] (composite active) gpio[18] (hsync) gpio[19] (hactive) gpio[20] (vsync) gpio[21] (vactive) gpio[22] (field) gpio[23] (clkx1) vdd numxtal xt0o xt0i bt848/848a/849a
bt848/848a/849a single-chip video capture for pci brook t ree 14 f unctional d escription pin assignments l848a_a table 3. bt848 pin list pin # pin name pin # pin name pin # pin name pin # pin name pin # pin name 1 vdd 33 vddp 65 cbe [0] 97 gpio[10] 129 n/c (1) 2 trst 34 gnd 66 ad[7] 98 gpio[9] (1) 130 vpos 3 tck 35 ad[19] 67 ad[6] 99 gpio[8] (1) 131 agccap 4 pvref 36 ad[18] 68 ad[5] 100 gnd 132 vneg 5 tms 37 ad[17] 69 ad[4] 101 vdd 133 refout 6 tdo 38 ad[16] 70 vddp 102 xt0i 134 vaa 7 tdi 39 cbe [2] 71 gnd 103 xt0o 135 agnd 8 int a 40 vdd 72 ad[3] 104 numxtal 136 vaa 9 rst 41 gnd 73 ad[2] 105 xt1i 137 yref+ 10 vddp 42 frame 74 ad[1] 106 xt1o 138 yin 11 clk 43 irdy 75 ad[0] 107 gnd 139 muxout 12 gnd 44 trdy 76 vddp 108 gpclk 140 agnd 13 gnt 45 devsel 77 gnd 109 vddg 141 mux0 14 req 46 stop 78 scl 110 gpio[7] 142 agnd 15 ad[31] 47 vddp 79 sda 111 gpio[6] 143 mux1 16 ad[30] 48 gnd 80 gnd 112 gpio[5] 144 agnd 17 ad[29] 49 perr 81 vdd 113 gpio[4] 145 mux2 18 vdd 50 serr 82 gpio[23] (1) 114 gpio[3] 146 agnd 19 gnd 51 par 83 gpio[22] (1) 115 gpio[2] 147 syncdet (1) 20 ad[28] 52 cbe [1] 84 gpio[21] (1) 116 gpio[1] 148 vaa 21 ad[27] 53 ad[15] 85 gpio[20] (1) 117 gpio[0] 149 agnd 22 ad[26] 54 ad[14] 86 gpio[19] (1) 118 gpwe 150 yref 23 ad[25] 55 ad[13] 87 gpio[18] (1) 119 gpintr 151 cref+ 24 ad[24] 56 vddp 88 gpio[17] (1) 120 vdd 152 vaa 25 vddp 57 gnd 89 gpio[16] (1) 121 gnd 153 agnd 26 gnd 58 ad[12] 90 vddg 122 gnd 154 cin 27 cbe [3] 59 ad[11] 91 gnd 123 vddg 155 agnd 28 idsel 60 ad[10] 92 gpio[15] 124 n/c (1) 156 vaa 29 ad[23] 61 ad[9] 93 gpio[14] 125 n/c (1) 157 cref 30 ad[22] 62 ad[8] 94 gpio[13] 126 n/c (1) 158 clevel 31 ad[21] 63 vdd 95 gpio[12] 127 n/c (1) 159 agnd 32 ad[20] 64 gnd 96 gpio[11] 128 n/c (1) 160 gnd notes: (1). alternate pin definitions on bt848a and bt849a.
brook t ree 15 f unctional d escription ultralock l848a_a bt848/848a/849a single-chip video capture for pci ultralock the challenge the line length (the interval between the midpoints of the falling edges of succeed- ing horizontal sync pulses) of analog video sources is not constant. for a stable source such as studio quality source or test signal generators, this variation is very small: 2 ns. however, for an unstable source such as a vcr, laser disk player, or tv tuner, line length variation is as much as a few microseconds. digital display systems require a ?ed number of pixels per line despite these variations. the bt848 employs a technique known as ultralock to implement locking to the horizontal sync and the subcarrier of the incoming analog video sig- nal and generating the required number of pixels per line. operation principles of ultralock ultralock is based on sampling using a ?ed-frequency, stable clock. since the video line length will vary, the number of samples generated using a ?ed-frequen- cy sample clock will also vary from line to line. if the number of generated samples per line is always greater than the number of samples per line required by the par- ticular video format, the number of acquired samples can be reduced to ? the re- quired number of pixels per line. the bt848 requires an 8*fsc (28.64 mhz for ntsc and 35.47 mhz for pal) crystal or oscillator input signal source. the 8*fsc clock signal, or clkx2, is di- vided down to clkx1 internally (14.32 mhz for ntsc and 17.73 mhz for pal). clkx2 and clkx1 are internal signals and are not made available to the system. ultralock operates at clkx1 although the input waveform is sampled at clkx2 then low pass ?tered and decimated to clkx1 sample rate. at a 4*fsc (clkx1) sample rate there are 910 pixels for ntsc and 1,135 pixels for pal/secam within a nominal line time interval (63.5 m s for ntsc and 64 m s for pal/secam). for square pixel ntsc and pal/secam formats, there should only be 780 and 944 pixels per video line, respectively. this is because the square pixel clock rates are slower than a 4*fsc clock rate, i.e., 12.27 mhz for ntsc and 14.75 mhz for pal. ultralock accommodates line length variations from nominal in the incoming video by always acquiring more samples, at an effective 4*fsc rate, than are re- quired by the particular video format and outputting the correct number of pixels per line. ultralock then interpolates the required number of pixels in a way that maintains the stability of the original image despite variation in the line length of the incoming analog waveform.
bt848/848a/849a single-chip video capture for pci brook t ree 16 f unctional d escription ultralock l848a_a the example illustrated in figure 4 shows three successive lines of video being decoded for square pixel ntsc output. the ?st line is shorter than the nominal ntsc line time interval of 63.5 m s. on this ?st line, a line time of 63.2 m s sampled at 4*fsc (14.32 mhz) generates only 905 pixels. the second line matches the nominal line time of 63.5 m s and provides the expected 910 pixels. finally, the third line is too long at 63.8 m s within which 913 pixels are generated. in all three cases, ultralock outputs only 780 pixels. ultralock can be used to extract any programmable number of pixels from the original video stream as long as the sum of the nominal pixel line length (910 for ntsc and 1,135 for pal/secam) and the worst case line length variation from nominal in the active region is greater than or equal to the required number of out- put pixels per line, i.e., it should be noted that, for stable inputs, ultralock guarantees the time between the falling edges of hreset only to within one pixel. ultralock does, however, guarantee the number of active pixels in a line as long as the above relationship holds. figure 4. ultralock behavior for ntsc square pixel output analog waveform 63.2 m s 63.5 m s 63.8 m s 905 pixels 910 pixels 913 pixels line length pixels per line 780 pixels 780 pixels 780 pixels pixels sent to the fifo by ultralock p nom p var +p desired 3 where: p nom = nominal number of pixels per line at 4*fsc sample rate (910 for ntsc, 1,135 for pal/secam) p var = variation of pixel count from nominal at 4*fsc (can be a positive or negative number) p desired = desired number of output pixels per line
17 f unctional d escription composite video input formats l848a_a bt848/848a/849a single-chip video capture for pci composite video input formats bt848 supports several composite video input formats. table 4 shows the different video formats and some of the countries in which each format is used. the video decoder must be programmed appropriately for each of the compos- ite video input formats. table 5 lists the register values that need to be programmed for each input format. table 4. video input formats supported by the bt848 format lines fields f sc ntsc-m 525 60 3.58 mhz ntsc-japan (1) 525 60 3.58 mhz pal-b 625 50 4.43 mhz pal-d 625 50 4.43 mhz pal-g 625 50 4.43 mhz pal-h 625 50 4.43 mhz pal-i 625 50 4.43 mhz pal-m 525 60 3.58 mhz pal-n combination 625 50 3.58 mhz pal-n 625 50 4.43 mhz secam 625 50 4.43 mhz notes:(1). ntsc-japan has 0 ire setup.
bt848/848a/849a single-chip video capture for pci brook t ree 18 f unctional d escription composite video input formats l848a_a table 5. register values for video input formats register bit ntsc-m ntsc-japan pal-b, d, g, h, i pal-m pal-n pal-n combination secam iform (0x01) xtsel [4:3] 01 01 10 01 10 01 10 format [2:0] 001 010 011 100 101 111 110 cropping: hdelay, vdelay, vactive, crop [7:0] in all ?e registers set to desired cropping values in registers set to ntsc-m square pixel values set to desired cropping values in registers set to ntsc-m square pixel values set to pal-b, d, g, h, i square pixel values hscale (0x08, 0x09) [15:0] 0x02ac 0x02ac 0x033c 0x02ac 0x033c 0x033c (1) 0x033c adelay (0x18) [7:0] 0x68 0x68 0x7f 0x68 0x7f 0x7f 0x7f bdelay (0x19) [7:0] 0x5d 0x5d 0x72 0x5d 0x72 0x72 tbd notes: (1). the bt848a and bt849a will not output square pixel resolution for pal n-combination. a smaller number of pixels must be output.
brook t ree 19 f unctional d escription y/c separation and chroma demodulation l848a_a bt848/848a/849a single-chip video capture for pci y/c separation and chroma demodulation y/c separation and chroma decoding are handled as shown in figure 5. bandpass and notch ?ters are implemented to separate the composite video stream. the ?- ter responses are shown in figure 6. the optional chroma comb ?ter is imple- mented in the vertical scaling block. see the video scaling, cropping, and temporal decimation section in this chapter. figure 7 schematically describes the ?tering and scaling operations. in addition to the y/c separation and chroma demodulation illustrated in figure 5, the bt848 also supports chrominance comb ?tering as an optional ?ter- ing stage after chroma demodulation. the chroma demodulation generates base- band i and q (ntsc) or u and v (pal/secam) color difference signals. for s-video operation, the digitized luma data bypasses the y/c separation block completely, and the digitized chrominance is passed directly to the chroma demodulator. for monochrome operation, the y/c separation block is also bypassed, and the saturation registers (sat_u and sat_v) are set to zero. figure 5. y/c separation and chroma demodulation for composite video notch filter band pass filter low pass filter low pass filter sin cos y u v composite
bt848/848a/849a single-chip video capture for pci brook t ree 20 f unctional d escription y/c separation and chroma demodulation l848a_a figure 6. y/c separation filter responses ntsc pal/secam ntsc pal/secam luma notch filter frequency responses for ntsc and pal/secam chroma band pass filter frequency responses for ntsc and pal/secam figure 7. filtering and scaling note: z? refers to a pixel delay in the horizontal direction, and a line delay in the vertical direction. the coefficients are determined by ultralock and the scaling algorithm chrominance 1 2 -- - 1 2 -- -z 1 + = luminance cdz 1 + = vertical scaler luminance abz 1 cz 2 dz 3 ez 4 fz 5 +++++ = chrominance ghz 1 + = horizontal scaler 6 tap, 32 phase interpolation on-chip memory and horizontal scaling 2 tap, 32 phase interpolation on-chip memory and and horizontal scaling chroma comb low pass filter y y c c optional horizontal vertical scaling luma comb (chroma comb) 3 mhz 1 4 -- -1 2 z 1 1 z 2 ++ () = 1 8 -- -1 3 z 1 3 z 2 1 z 3 +++ () = 1 16 ------ 1 4 z 1 6 z 2 4 z 3 z 4 ++++ () = vertical filter options vertical scaling vertical filtering luminance 1 2 -- -1 z 1 + () =
brook t ree 21 f unctional d escription video scaling, cropping, and temporal decimation l848a_a bt848/848a/849a single-chip video capture for pci video scaling, cropping, and temporal decimation the bt848 provides three mechanisms to reduce the amount of video pixel data in its output stream; down-scaling, cropping, and temporal decimation. all three can be controlled independently. horizontal and vertical scaling the bt848 provides independent and arbitrary horizontal and vertical down scal- ing. the maximum scaling ratio is 16:1 in both x and y dimensions. the maxi- mum vertical scaling ratio is reduced from 16:1 when using frames to 8:1 when using ?lds. the different methods utilized for scaling luminance and chromi- nance are described in the following sections. luminance scaling the ?st stage in horizontal luminance scaling is an optional pre-?ter which pro- vides the capability to reduce anti-aliasing artifacts. it is generally desirable to lim- it the bandwidth of the luminance spectrum prior to performing horizontal scaling because the scaling of high-frequency components may create image artifacts in the resized image. the optional low pass ?ters shown in figure 8 reduce the hor- izontal high-frequency spectrum in the luminance signal. figure 9 and figure 10 show the combined results of the optional low-pass ?ters, the luma notch ?ter and the 2x oversampling ?ter. figure 12 shows the combined responses of the luma notch ?ter and the 2x oversampling ?ter. the bt848 implements horizontal scaling through poly-phase interpolation. the bt848 uses 32 different phases to accurately interpolate the value of a pixel. this provides an effective pixel jitter of less than 6 ns. in simple pixel- and line-dropping algorithms, non-integer scaling ratios intro- duce a step function in the video signal that effectively introduces high-frequency spectral components. poly-phase interpolation accurately interpolates to the cor- rect pixel and line position providing more accurate information. this results in aesthetically pleasing video as well as higher compression ratios in bandwidth lim- ited applications. for vertical scaling, the bt848 uses a line store to implement four different ?- tering options. the ?ter characteristics are shown in figure 11. the bt848 pro- vides up to 5-tap ?tering to ensure removal of aliasing artifacts. the number of taps in the vertical ?ter is set by the vtc register. the user may select 2, 3, 4 or 5 taps. the number of taps must be chosen in conjunction with the horizontal scale factor in order to ensure the needed data can ? in the internal fifo (see the vfilt bits in the vtc register for limitations). as the scaling ratio is increased, the number of taps available for vertical scaling is increased. in addi- tion to low-pass ?tering, vertical interpolation is also employed to minimize arti- facts when scaling to non-integer scaling ratios.
bt848/848a/849a single-chip video capture for pci brook t ree 22 f unctional d escription video scaling, cropping, and temporal decimation l848a_a figure 8. optional horizontal luma low-pass filter responses ntsc pal/secam icon qcif cif icon qcif cif figure 9. combined luma notch, 2x oversampling and optional low-pass filter response (ntsc) icon qcif cif icon qcif cif pass band full spectrum figure 10. combined luma notch, 2x oversampling and optional low-pass filter response (pal/secam) icon qcif cif icon qcif cif pass band full spectrum
brook t ree 23 f unctional d escription video scaling, cropping, and temporal decimation l848a_a bt848/848a/849a single-chip video capture for pci figure 11. frequency responses for the four optional vertical luma low-pass filters 2-tap 3-tap 4-tap 5-tap figure 12. combined luma notch and 2x oversampling filter response ntsc pal/secam
bt848/848a/849a single-chip video capture for pci brook t ree 24 f unctional d escription video scaling, cropping, and temporal decimation l848a_a peaking (bt848a and bt849a only) the bt848a enables four different peaking levels by programming the peak bit and hfilt bits in the scloop register. the ?ters are shown in figures 13 and 14. figure 13. peaking filters (bt848a/849a only) hfilt = 00 hfilt = 11 hfilt = 10 hfilt = 01 hfilt = 00 hfilt = 10 hfilt = 11 hfilt = 01 enhanced resolution of passband
brook t ree 25 f unctional d escription video scaling, cropping, and temporal decimation l848a_a bt848/848a/849a single-chip video capture for pci figure 14. luma peaking filters with 2x oversampling filter and luma notch (bt848a/849a only) hfilt = 00 hfilt = 11 hfilt = 01 hfilt = 10 hfilt = 00 hfilt = 10 hfilt = 11 hfilt = 01 enhanced resolution of passband
bt848/848a/849a single-chip video capture for pci brook t ree 26 f unctional d escription video scaling, cropping, and temporal decimation l848a_a chrominance scaling a 2-tap, 32-phase interpolation ?ter is used for horizontal scaling of chrominance. vertical scaling of chrominance is implemented through chrominance comb ?ter- ing using a line store, followed by simple decimation or line dropping. scaling registers the horizontal scaling ratio register (hscale) is programmed with the hor- izontal scaling ratio. when outputting unscaled video (in ntsc), the bt848 will produce 910 pixels per line. this corresponds to the pixel rate at f clkx1 (4*fsc). this register is the control for scaling the video to the desired size. for example, square pixel ntsc requires 780 samples per line, while ccir601 requires 858 samples per line. hscale_hi and hscale_lo are two 8-bit registers that, when concatenated, form the 16-bit hscale register. the method below uses pixel ratios to determine the scaling ratio. the follow- ing formula should be used to determine the scaling ratio to be entered into the 16-bit register: for example, to scale pal/secam input to square pixel qcif, the total number of horizontal pixels desired is 236: an alternative method for determining the hscale value uses the ratio of the scaled active region to the unscaled active region as shown below: in this equation, the hactive value cannot be cropped; it represents the total ac- tive region of the video line. this equation produces roughly the same result as us- ing the full line length ratio shown in the ?st example. however, due to truncation, the hscale values determined using the active pixel ratio method will be slightly different than those obtained using the total line length pixel ratio method. the val- ues in table 6 were calculated using the full line length ratio. ntsc: hscale = [ ( 910/p desired ) ?1] * 4096 pal/secam: hscale = [ ( 1135/p desired ) ?1] * 4096 where: p desired = desired number of pixels per line of video, includ- ing active, sync and blanking. hscale = [ ( 1135/236 ) ?1 ] * 4096 = 12331 = 0x3cf2 ntsc: hscale = [ (754 / hactive) ?1] * 4096 pal/secam: hscale = [ (922 / hactive) ?1] * 4096 where: hactive = desired number of pixels per line of video, not in- cluding sync or blanking.
brook t ree 27 f unctional d escription video scaling, cropping, and temporal decimation l848a_a bt848/848a/849a single-chip video capture for pci the vertical scaling ratio register (vscale) is programmed with the ver- tical scaling ratio. it de?es the number of vertical lines output by the bt848. the following formula should be used to determine the value to be entered into this 13-bit register. the loaded value is a twos-complement, negative value. for example, to scale pal/secam input to square pixel qcif, the total number of vertical lines is 156: note that only the 13 least signi?ant bits of the vscale value are used; the ?e lsbs of vscale_hi and the 8-bit vscale_lo register form the 13-bit vs- cale register. the three msbs of vscale_hi are used to control other func- tions. the user must take care not to alter the values of the three most signi?ant bits when writing a vertical scaling value. the following c-code fragment illus- trates changing the vertical scaling value: #define byte unsigned char #define word unsigned int #define vscale_hi 0x13 #define vscale_lo 0x14 byte readfrombt848( byte regaddress ); void writetobt848( byte regaddress, byte regvalue ); void setbt848vscaling( word vscale ) { byte oldvscalemsbyte, newvscalemsbyte; /* get existing vscalemsbyte value from */ /* bt848 vscale_hi register */ oldvscalemsbyte = readfrombt848( vscale_hi ); /* create a new vscalemsbyte, preserving top 3 bits */ newvscalemsbyte = (oldvscalemsbyte & 0xe0) | (vscale >> 8); /* send the new vscalemsbyte to the vscale_hi reg */ writetobt848( vscale_hi, newvscalemsbyte ); /* send the new vscalelsbyte to the vscale_lo reg */ writetobt848( vscale_lo, (byte) vscale ); } if your target machine has suf?ient memory to statically store the scaling val- ues locally, the read operation can be eliminated. vscale = ( 0x10000 ?{ [ ( scaling_ratio ) ?1] * 512 } ) & 0x1fff vscale = ( 0x10000 ?{ [ ( 4/1 ) ? ] * 512 } ) & 0x1fff = 0x1a00 where: & = bitwise and | = bitwise or >> = bit shift, msb to lsb
bt848/848a/849a single-chip video capture for pci brook t ree 28 f unctional d escription video scaling, cropping, and temporal decimation l848a_a note on vertical scaling: when scaling below cif resolution, it may be useful to use a single ?ld as opposed to using both ?lds. using a single ?ld will ensure there are no inter-?ld motion artifacts on the scaled output. when performing sin- gle ?ld scaling, the vertical scaling ratio will be twice as large as when scaling with both ?lds. for example, cif scaling from one ?ld does not require any ver- tical scaling, but when scaling from both ?lds, the scaling ratio is 50%. also, the non-interlaced bit should be reset when scaling from a single ?ld (int=0 in the vscale_hi register). table 6 lists scaling ratios for various video formats, and the register values required. image cropping cropping enables the user to output any subsection of the video image. the ac- tive ?g can be programmed to start and stop at any position on the video frame as shown in figure 15. the start of the active area in the vertical direction is refer- enced to vreset (beginning of a new ?ld). in the horizontal direction it is ref- erenced to hreset (beginning of a new line). the dimensions of the active video region are de?ed by hdelay, hactive, vdelay, and vactive. all four registers are 10-bit values. the two msbs of each register are contained in the crop register, while the lower eight bits are in the respective hdelay_lo, hactive_lo, vdelay_lo and vactive_lo registers. the vertical and hor- izontal delay values determine the position of the cropped image within a frame while the horizontal and vertical active values set the pixel dimensions of the cropped image as illustrated in figure 15. table 6. scaling ratios for popular formats using frequency values scaling ratio format total resolution (including sync and blanking interval) output resolution (active pixels) hscale register values vscale register values use both fields single field full resolution 1:1 ntsc sq pixel ntsc ccir601 pal ccir601 pal sq pixel 780x525 858x525 864x625 944x625 640x480 720x480 720x576 768x576 0x02aa 0x00f8 0x0504 0x033c 0x0000 0x0000 0x0000 0x0000 n/a n/a n/a n/a cif 2:1 ntsc sq pixel ntsc ccir601 pal ccir601 pal sq pixel 390x262 429x262 432x312 472x312 320x240 360x240 360x288 384x288 0x1555 0x11f0 0x1a09 0x1679 0x1e00 0x1e00 0x1e00 0x1e00 0x0000 0x0000 0x0000 0x0000 qcif 4:1 ntsc sq pixel ntsc ccir601 pal ccir601 pal sq pixel 195x131 214x131 216x156 236x156 160x120 180x120 180x144 192x144 0x3aaa 0x3409 0x4412 0x3cf2 0x1a00 0x1a00 0x1a00 0x1a00 0x1e00 0x1e00 0x1e00 0x1e00 icon 8:1 ntsc sq pixel ntsc ccir601 pal ccir601 pal sq pixel 97x65 107x65 108x78 118x78 80x60 90x60 90x72 96x72 0x861a 0x7813 0x9825 0x89e5 0x1200 0x1200 0x1200 0x1200 0x1a00 0x1a00 0x1a00 0x1a00
brook t ree 29 f unctional d escription video scaling, cropping, and temporal decimation l848a_a bt848/848a/849a single-chip video capture for pci figure 15. effect of the cropping and active registers beginning of a new frame beginning of a new line video frame horizontally active horizontally inactive vertically vertically video frame horizontally horizontally inactive vertically vertically cropped image cropped image scaled to 1/2 size active inactive active inactive active hreset vreset
bt848/848a/849a single-chip video capture for pci brook t ree 30 f unctional d escription video scaling, cropping, and temporal decimation l848a_a cropping registers the horizontal delay register (hdelay) is programmed with the delay be- tween the falling edge of hreset and the rising edge of active. the count is programmed with respect to the scaled frequency clock. note that hdelay should always be an even number. the horizontal active register (hactive) is programmed with the actual number of active pixels per line of video. this is equivalent to the number of scaled pixels that the bt848 should output on a line. for example, if this register contained 90, and hscale was programmed to downscale by 4:1, then 90 active pixels would be output. the 90 pixels would be a 4:1 scaled image of the 360 pixels (at clkx1) starting at count hdelay. hactive is restricted in the following man- ner: hactive + hdelay total number of scaled pixels. for example, in the ntsc square pixel format, there is a total of 780 pixels, in- cluding blanking, sync and active regions. therefore: hactive + hdelay 780. when scaled by 2:1 for cif, the total number of active pixels is 390. therefore: hactive +hdelay 390. the hdelay register is programmed with the number of scaled pixels be- tween hreset and the ?st active pixel. because the front porch is de?ed as the distance between the last active pixel and the next horizontal sync, the video line can be considered in three components: hdelay, hactive and the front porch. see figure 16. when cropping is not implemented, the number of clocks at the 4x sample rate (the clkx1 rate) in each of these regions is shown below: the value for hdelay is calculated using the following formula: hdelay = [(clkx1_hdelay / clkx1_hactive) * hactive] & 0x3fe clkx1_hdelay and clkx1_hactive are constant values, so the equation becomes: ntsc:hdelay = [(135 / 754) * hactive] & 0x3fe pal/secam:hdelay = [(186 / 922) * hactive] & 0x3fe in this equation, the hactive value cannot be cropped. clkx1 front porch clkx1 hdelay clkx1 hactive clkx1 total ntsc 21 135 754 910 pal/secam 27 186 922 1135
brook t ree 31 f unctional d escription video scaling, cropping, and temporal decimation l848a_a bt848/848a/849a single-chip video capture for pci the vertical delay register (vdelay) is programmed with the delay be- tween the rising edge of vreset and the start of active video lines. it determines how many lines to skip before initiating the active signal. it is programmed with the number of lines to skip at the beginning of a frame. the vertical active register (vactive) is programmed with the number of lines used in the vertical scaling process. the actual number of vertical lines output from the bt848 is equal to this register times the vertical scaling ratio. if vscale is set to 0x1a00 (4:1) then the actual number of lines output is vactive/4. if vs- cale is set to 0x0000 (1:1) then vactive contains the actual number of vertical lines output. note: it is important to note the difference between the implementation of the horizontal registers (hscale, hdelay, and hactive) and the vertical regis- ters (vscale, vdelay, and vactive). horizontally, hdelay and hac- tive are programmed with respect to the scaled pixels de?ed by hscale. vertically, vdelay and vactive are programmed with respect to the number of lines before scaling (before vscale is applied). temporal decimation temporal decimation provides a solution for video synchronization during periods when full frame rate can not be supported due to bandwidth and system restric- tions. for example, when capturing live video for storage, system limitations such as hard disk transfer rates or system bus bandwidth may limit the frame capture rate. if these restrictions limit the frame rate to 15 frames per second, the bt848s time scaling operation will enable the system to capture every other frame instead of al- lowing the hard disk timing restrictions to dictate which frame to capture. this maintains an even distribution of captured frames and alleviates the ?erky?effects caused by systems that simply burst in data when the bandwidth becomes avail- able. the bt848 provides temporal decimation on either a ?ld or frame basis. the temporal decimation register (tdec) is loaded with a value from 1 to 60 (ntsc) or 1 to 50 (pal/secam). this value is the number of ?lds or frames skipped by the chip during a sequence of 60 for ntsc or 50 for pal/secam. skipped ?lds and frames are considered inactive, which is indicated by the active pin remain- ing low. figure 16. regions of the video signal hdelay hactive front porch
bt848/848a/849a single-chip video capture for pci brook t ree 32 f unctional d escription video scaling, cropping, and temporal decimation l848a_a examples: when changing the programming in the temporal decimation register, 0x00 should be loaded ?st, and then the decimation value. this will ensure that the decimation counter is reset to zero. if zero is not ?st loaded, the decimation may start on any ?ld or frame in the sequence of 60 (or 50 for pal/secam). on power-up, this preload is not necessary because the counter is internally reset. when decimating ?lds, the fldalign bit in the tdec register can be pro- grammed to choose whether the decimation starts with an odd ?ld or an even ?ld. if the fldalign bit is set to logical zero, the ?st ?ld that is dropped dur- ing the decimation process will be an odd ?ld. conversely, setting the fldalign bit to logical one causes the even ?ld to be dropped ?st in the dec- imation process. tdec = 0x02 decimation is performed by frames. two frames are skipped per 60 frames of video, assuming ntsc decoding. frames 1?9 are output normally, then ac- tive remains low for one frame. frames 31?9 are then output followed by another frame of in- active video. tdec = 0x9e decimation is performed by fields. thirty fields are output per 60 fields of video, assuming ntsc decoding. this value outputs every other ?ld (every odd ?ld) of video starting with ?ld one in frame one. tdec = 0x01 decimation is performed by frames. one frame is skipped per 50 frames of video, assuming pal/secam decoding. tdec = 0x00 decimation is not performed. full frame rate video is output by the bt848.
brook t ree 33 f unctional d escription video adjustments l848a_a bt848/848a/849a single-chip video capture for pci video adjustments the bt848 provides programmable hue, contrast, saturation, and brightness. the hue adjust register (hue) the hue adjust register is used to offset the hue of the decoded signal. in ntsc, the hue of the video signal is de?ed as the phase of the subcarrier with reference to the burst. the value programmed in this register is added to or subtracted from the phase of the subcarrier, which effectively changes the hue of the video. the hue can be shifted by plus or minus 90 degrees. because of the nature of pal/secam encoding, hue adjustments can not be made when decoding pal/secam. the contrast adjust register (contrast) the contrast adjust register (also called the luma gain) provides the ability to change the contrast from approximately 0% to 200% of the original value. the de- coded luma value is multiplied by the 9-bit coef?ient loaded into this register. the saturation adjust registers (sat_u, sat_v) the saturation adjust registers are additional color adjustment registers. it is a multiplicative gain of the u and v signals. the value programmed in these regis- ters are the coef?ients for the multiplication. the saturation range is from approx- imately 0% to 200% of the original value. the brightness register (bright) the brightness register is simply an offset for the decoded luma value. the pro- grammed value is added to or subtracted from the original luma value which changes the brightness of the video output. the luma output is in the range of 0 to 255. brightness adjustment can be made over a range of ?28 to +127. automatic chrominance gain control the automatic chrominance gain control compensates for reduced chrominance and color-burst amplitudes. here, the color-burst amplitude is calculated and com- pared to nominal. the color-difference signals are then increased or decreased in amplitude according to the color-burst amplitude difference from nominal. the range of chrominance gain is 0.5? times the original amplitude. this compensa- tion coef?ient is then multiplied by the saturation adjust value for a total chromi- nance gain range of 0? times the original signal. automatic chrominance gain control may be disabled.
bt848/848a/849a single-chip video capture for pci brook t ree 34 f unctional d escription low color detection and removal l848a_a low color detection and removal if a color-burst of 25 percent (ntsc) or 35 percent (pal/secam) or less of the nominal amplitude is detected for 127 consecutive scan lines, the color-difference signals u and v are set to zero. when the low color detection is active, the reduced chrominance signal is still separated from the composite signal to generate the lu- minance portion of the signal. the resulting cr and cb values are 128. output of the chrominance signal is re-enabled when a color-burst of 43 percent (ntsc) or 60 percent (pal/secam) or greater of nominal amplitude is detected for 127 con- secutive scan lines. low color detection and removal may be disabled. coring the bt848 video decoder can perform a coring function, in which it forces all val- ues below a programmed level to be zero. this is useful because the human eye is more sensitive to variations in black images. by taking near black images and turn- ing them into black, the image appears clearer to the eye. four coring values can be selected: 0, 8, 16, or 32 above black. if the total lu- minance level is below the selected limit, the luminance signal is truncated to the black value. if the luma range is limited (i.e. black is 16), then the coring circuitry automatically takes this into account and references the appropriate value for black. coring is illustrated in figure 17. figure 17. coring map 32 16 8 0 32 16 8 0 calculated luma value output luma value
brook t ree 35 f unctional d escription vbi data output interface l848a_a bt848/848a/849a single-chip video capture for pci vbi data output interface a frame of video is composed of 525 lines for nstc and 625 for pal/secam. figure 18 illustrates an ntsc video frame, in which there are a number of distinct regions. the video image or picture data is contained in the odd and even ?lds within lines 21 to 263 and lines 283 to 525 respectively. each ?ld of video also contains a region for vertical synchronization (lines 1 through 9 and 263 through 272) as well as a region which can contain non-video ancillary data (lines 10 through 20 and 272 through 283). we will refer to these regions which are between the vertical synchronization region and the video picture region as the vertical blanking interval or vbi portion of the video signal. the bt848 is able to capture vbi data and store it in the host memory for later pro- cessing by the bt848 vbi decoder software. two modes of vbi capture exist: vbi line output mode and vbi frame output mode. both types of data may be captured during the same ?ld. in the vbi line output mode, vbi capture occurs during the vertical blanking in- terval. the start of vbi data capture is set by the vbi_hdelay bit in the vbi packet size/delay register, and is in reference to the trailing edge of the hreset signal. the number of dwords of vbi data is selected by the user. each dword contains 4 vbi bytes, and each vbi pixel consists of two vbi samples. for example, for a given 800 pixel line in the vbi region, there exist 1600 vbi samples, which is equivalent to 400 dwords of vbi data. the vbi_pkt_hi and vbi_pkt_lo register bits are concatenated to create the 9-bit value for the num- ber of dwords to be captured. figure 18. regions of the video frame lines 1? lines 10?0 lines 21?63 lines 263?72 lines 272?83 lines 283?25 vertical blanking interval video image region vertical blanking interval video image region odd field even field vertical synchronization region vertical synchronization region
bt848/848a/849a single-chip video capture for pci brook t ree 36 f unctional d escription vbi data output interface l848a_a vbi line data capture occurs when the capture_even register bit is en- abled for the even ?ld and capture_odd register bit is enabled for the odd ?ld. the vbi data is sampled at a rate of 8*fsc and is stored in the fifo as a se- quence of 8-bit samples. line mode vbi data is horizontally bound beginning at vbi_hdelay pixels from the trailing edge of hreset and ending after the vbi_pkt number of dwords. line mode vbi data is vertically bound starting at the ?st line following vreset and ending at vactive. vbi register settings can only be changed on a per frame basis. the vbi timing is illustrated in figure 19. once the vbi data has been captured and stored in the bt848 fifo, it is treated as any other type of data. it is output over the pci bus via risc instructions. if the number of vbi lines desired by the user is smaller than the entire vertical blanking region, the extra data will be discarded by the use of the skip risc instruction. alternatively, if the user desires a larger vbi region in the vbi line output mode, the vertical blanking region can be extended by setting the vdelay register bit to the appropriate value. the vbi line output mode can in effect extend the vbi re- gion to the entire ?ld. figure 20 shows a block diagram of the vbi section. figure 19. vbi timing vbi line data capture vbi_pkt # vbi_hdelay vdelay vactive vreset hreset figure 20. vbi section block diagram ycrcb 4:2:2, 4:1:1 csc/gamma 8-bit dither format mux fifos y: 70x36 cb: 35x36 cr: 35x36 # dwords dma controller pci initiator instruction queue address generator fifo data mux pci video data format converter bus vbi data analog video adc
brook t ree 37 f unctional d escription vbi data output interface l848a_a bt848/848a/849a single-chip video capture for pci in the vbi frame output mode, the vbi data capture occurs in the active video region and includes all the horizontal blank/sync information in the data stream. the data is vertically bound beginning at the ?st line during vactive and ending after a ?ed number of packets. the data stream is packetized into a series of 256-dword blocks. a ?ed number of dword blocks (434 for ntsc and 650 for pal) are cap- tured during each ?ld. this is equivalent to 111,104 dwords for ntsc (434 * 256 dwords) and 166,400 dwords for pal (650 * 256 dwords) per ?ld. the vbi frame capture region may be extended to include the 10 lines prior to the default vactive region by setting the ext_frame register bit. vdelay must also be set to its minimum value of 2. the extended dword block size is 450 dword blocks for ntsc and 674 dword blocks for pal. the vbi frame data capture occurs during the even ?ld when the capture_even register bit is set and the color_even bit is set to raw mode, and during the odd ?ld when the capture_odd register bit is set and the color_odd bit is set to raw mode. the captured data stream is continuous and not aligned with hsync.
bt848/848a/849a single-chip video capture for pci brook t ree 38 f unctional d escription video data format conversion l848a_a video data format conversion pixel data path the video decoder/scaler portion of the bt848 generates a video data stream in packed 4:2:2 ycrcb format. the video data is then color space converted and for- matted in a 32-bit wide dword. figure 21 shows the steps in converting the vid- eo data from packed 4:2:2 ycrcb to the desired format. the ycrcb 4:2:2 data is up-sampled to 4:4:4 format prior to conversion to rgb. it can then be dithered, have gamma correction removed, or be presented directly to the byte swap circuit. in the case where 4:1:1 data is desired, the 4:2:2 data is ?st down sampled, then packed into btyuv format or converted to planar format and vertically subsam- pled to achieve the yuv9 format. alternatively, packed 4:2:2 data may be convert- ed to planar 4:2:2 and vertically sub-sampled to yuv12 format. the vertical subsampling is achieved via the appropriate dma instructions (see the dma con- troller section). bt848 also offers a y8 color format, in which the chroma component of the packed 4:2:2 data is stripped and the luma component is packed into 8 bits. this format is otherwise known as gray scale. table 7 shows the various color formats supported by the bt848 and the mapping of the bytes onto 32-bit dwords. video control code status data in addition to the pixel information, the bt848s video data format converter pro- vides four bits of video control status code to the fifo. these four bits of status code status[3:0] are based on inputs from the video decoder/scaler block of the bt848, and convey information about the pixel data and the state of the video tim- ing (figure 21). status[3:0] are used to specify the fifo mode (packed or pla- nar), provide information regarding the pixel data (respective position of the pixel and number of valid bytes), to indicate if the pixel data is valid, and to signal the end of a capture enabled ?ld. see table 9 in the fifo section for a full list of the status codes and descriptions.
brook t ree 39 f unctional d escription video data format conversion l848a_a bt848/848a/849a single-chip video capture for pci figure 21. video data format converter up-sample chroma color space conversion strip chroma and pack luma sub-sample chroma packed to planar conversion gamma removal dither video packed to planar conversion control code generator vertical sub-sample chroma dma linear rgb y8 (gray scale) btyuv planar 4:1:1 planar 4:1:1 planar 4:2:2 8-bit dithered fi[31:0] planar planar packed 4:2:2 packed 4:1:1 4:4:4 status[3:0] fifo write signals fifo write clock packed 4:2:2 packed 4:2:2 fi[35:32] internal control signals from bt848 video decoder from bt848 video decoder/scaler planar 4:2:2 to fifo to fifo byte swap rgb rgb controller from fifo yuv9 yuv12 correction
bt848/848a/849a single-chip video capture for pci brook t ree 40 f unctional d escription video data format conversion l848a_a table 7. color formats format dword pixel data [31:0] byte lane 3 [31:24] byte lane 2 [23:16] byte lane 1 [15:8] byte lane 0 [7:0] rgb32 (1) dw0 alpha r g b rgb24 dw0 b1 r0 g0 b0 dw1 g2 b2 r1 g1 dw2 r3 g3 b3 r2 rgb16 dw0 {r1[7:3],g1[7:2],b1[7:3]} {r0[7:3],g0[7:2],b0[7:3]} rgb15 dw0 {0,r1[7:3],g1[7:3],b1[7:3]} {0,r0[7:3],g0[7:3],b0[7:3]} yuy2?crcb 4:2:2 (2) dw0 cr0 y1 cb0 y0 dw1 cr2 y3 cb2 y2 btyuv?crcb 4:1:1 dw0 y1 cr0 y0 cb0 dw1 y3 cr4 y2 cb4 dw2 y7 y6 y5 y4 y8 (gray scale) dw0 y3 y2 y1 y0 8-bit dithered dw0 b3 b2 b1 b0 vbi data dw0 d3 d2 d1 d0 ycrcb 4:2:2 planar dw0 fifo1 y3 y2 y1 y0 dw1 fifo1 y7 y6 y5 y4 dw0 fifo2 cb6 cb4 cb2 cb0 dw0 fifo3 cr6 cr4 cr2 cr0 yuv12 planar vertically sub-sampled to 4:2:2 by the dma controller ycrcb 4:1:1 planar dw0 fifo1 y3 y2 y1 y0 dw1 fifo1 y7 y6 y5 y4 dw2 fifo1 y11 y10 y9 y8 dw3 fifo1 y15 y14 y13 y12 dw0 fifo2 cb12 cb8 cb4 cb0 dw0 fifo3 cr12 cr8 cr4 cr0 yuv9 planar vertically sub-sampled to 4:1:1 by the dma controller notes: (1). the alpha byte can be written as 0 data, or not written. (2). uyvy can be achieved by byte swapping.
brook t ree 41 f unctional d escription video data format conversion l848a_a bt848/848a/849a single-chip video capture for pci ycrcb to rgb conversion the 4:2:2 ycrcb data stream from the video decoder portion of the bt848 must be converted to 4:4:4 ycrcb before the rgb conversion occurs, using an interpola- tion ?ter on the chroma data path. the even valid chroma data pass through un- modi?d, while the odd data is generated by averaging adjacent even data. the chroma component is upsampled using the following equations: for n = 0, 2, 4, etc. cb n = cb n cr n = cr n cb n+1 = (cb n + cb n+2 )/2 cr n+1 = (cr n + cr n+2 )/2 rgb conversion: r = 1.164(y?6) + 1.596(cr?28) g = 1.164(y?6) ?0.813(cr?28) ?0.391(cb?28) b = 1.164(y?6) + 2.018(cb?28) y range = [16,235] cr/cb range = [16,240] rgb range = [0,255] gamma correction removal bt848 provides gamma correction removal capability. the available gamma values are: ntsc: rgbout = rgbin 2.2 pal: rgbout = rgbin 2.8 gamma correction removal capability is not programmable on a ?ld basis. furthermore, gamma correction removal is not available when ycrcb data is out- put. ycrcb sub-sampling the 4:2:2 data stream is horizontally sub-sampled to 4:1:1 using the following equations: for n = 0, 4, 8, etc.: cb n = (cb n + cb n+2 ) cr n = (cr n + cr n+2 ) vertical sub-sampling is supported by bt848s yuv9 and yuv12 planar modes. in these modes, the video data is ?st planarized and placed in the fifo as 4:2:2 planar or 4:1:1 planar data. the fifo data is then vertically sub-sampled to 4:1:1 for yuv9 and 4:2:2 for yuv12 formats. the vertical sub-sampling is per- formed via risc instructions that are executed by the dma controller. table 7 shows an example of a 4 pixel line for yuv9 and yuv12 formats. in the yuv12 format. line 2 of cr/cb data is discarded and hence 4:2:2 vertical sub-sampling is achieved. in the yuv9 format, lines 2? of cr/cb data are dis- carded and hence 4:1:1 vertical sub-sampling is achieved.
bt848/848a/849a single-chip video capture for pci brook t ree 42 f unctional d escription video data format conversion l848a_a byte swapping before the data enters the fifo it passes through a 4-way mux to allow swapping of the bytes to support macintosh (big endian) color data formats. the pixel dword pd[31:0] maps onto the fifo input fi[31:0]. the byte-swap mux remaps the data bytes, but byte lane 0 or bits[7:0] will still be considered the ?st byte of the scan line. table 8. byte swapping map word swap 0 1 byte swap 0 1 0 1 fifo inputs outputs of fifo data formatter [31:24] [31:24] [23:16] [15:8] [7:0] [23:16] [23:16] [31:24] [7:0] [15:8] [15:8] [15:8] [7:0] [31:24] [23:16] [7:0] [7:0] [15:8] [23:16] [31:24] note: the byte swapping mode is disabled during vbi data.
brook t ree 43 f unctional d escription video and control data fifo l848a_a bt848/848a/849a single-chip video capture for pci video and control data fifo the fifo block accepts data from the video data format conversion process, buff- ers the data in fifo memory, then outputs dwords to the dma controller to be burst onto the pci bus. logical organization the 630-byte data fifo is logically organized into 3 segments: fifo1 = 70 words deep by 36 bits wide, fifo2 = 35 x 36 bits, and fifo3 = 35 x 36 bits. each of the 140 fifo data words provide for one dword of pixel data and four bits of video control code status. this is illustrated in figure 22. the fifos are large enough to support ef?ient size burst transfers (16 to 32 data phases) in planar as well as packed mode. figure 22. data fifo block diagram fifo1 70x36 fifo2 35x36 fifo3 35x36 y cr cb fifo write signals (from vdfc) fifo enable signal (from control fifo write clock (synchronous to video decoder fifo1 output fifo2 output fifo3 output fifo read signals (from dma controller) fifo read clock (synchronous to pci clock) from fifo input data formatter fi[35:32] control status code fi[31:0] pixel data pixel clock) 3 3 register)
bt848/848a/849a single-chip video capture for pci brook t ree 44 f unctional d escription video and control data fifo l848a_a fifo data interface loading data into the fifo can begin only when valid pixels are present during the even or the odd ?ld. the pixel dword pd[31:0] is stored in fi[31:0], and the video control code status[3:0] is stored in fi[35:32]. the vbi data will be in- cluded in the captured sequence if vbi capture capability is enabled. the four bits of status are used to encode information about the pixel data and the state of the video timing unit (see table 9). video timing and control infor- mation are passed through the fifo along with the data stream. the fifo buffer isolates the asynchronous video input and pci output domains. control of the in- put stream can only occur from the video timing unit of the video decoder and from the con?ured registers. the interaction and synchronization of the dma control- ler and the risc instruction sequence will rely solely on the output side of the fifo. capturing data to the fifo always begins with a fifo mode indicator code fol- lowed by pixel data. the fifo mode indicator is to be stored in the fifos at the beginning of every capture-enabled ?ld, when the data format is changed mid-?ld such as transitioning from packed vbi data to planar mode, and when video capture of a ?ld is asynchronously enabled. the mode status codes are al- ways stored in planar format. fifo1 receives two copies of the status code, while fifo2 and fifo3 each receive one copy. the sol code is packed in the fifo with the ?st valid pixel data byte, which is the ?st pixel dword for the scan line. the eol code is packed in the fifo with the last valid pixel data byte, which is the last dword location written to the fifo for the scan line. the eol code indicates one to four valid bytes. the vre/vro code is stored in the fifo at the end of a capture-enabled ?ld. the dma controller activates the appropriate pci byte enables by the time a given dword arrives on the output side of the fifo. table 9. status bits status[3:0] description 0110 fm1 fifo mode: packed data to follow 1110 fm3 fifo mode: planar data to follow 0010 sol first active pixel/data dword of scan line 0001 eol last active pixel/data dword of scan line, 4 valid bytes 1101 eol last active pixel/data dword of scan line, 3 valid bytes 1001 eol last active pixel/data dword of scan line, 2 valid bytes 0101 eol last active pixel/data dword of scan line, 1 valid byte 0100 vre vreset following an even ?ld?alling edge of field 1100 vro vreset following an odd ?ld?ising edge of field 0000 pxv valid pixel/data dword
brook t ree 45 f unctional d escription video and control data fifo l848a_a bt848/848a/849a single-chip video capture for pci the dma controller will guarantee that the fifo does not ?l, therefore the vdfc has no responsibility for fifo overruns. the dma controller will be able to resynchronize to data streams that are shorter or longer than expected. note that planar mode and packed mode data can be present in the fifos at the same time if a bus access latency persists across a field transition, or if packed vbi data proceeds planar ycrcb data. physical implementation the three fifo outputs are delivered in parallel so that the dma controller can monitor the fifos and perform skipping (reading and discarding data), if neces- sary, on all three simultaneously. due to the latency in determining the number of dwords placed in each fifo, a fifo full (ffull) condition is indicated prior to the fifo count reach- ing the maximum fifo size. the fifo is considered ffull when the fifo count (fcnt) value equals or exceeds the ffull value. a read must occur on the same cycle as ffull, otherwise data will over?w and will be overwritten. the maximum bus latencies for various video formats and modes are shown in table 10. fifo input/output rates the input and output ports of the bt848s fifo can operate simultaneously and are asynchronous to one another. the maximum fifo input rate would be for consecutive writes of pal video at 17.73 mhz. however, there will never be consecutive-pixel-cycle writes to the same fifo. the fastest fifo write sequence is f1, f2, f1, f3. therefore, the fast- est write rate to any fifo is less than or equal to half of the pixel rate. the maximum fifo output read rate is one fifo word at the pci clock rate (33 mhz). all three fifos can be read simultaneously. some bus systems may be de- signed with pci clocks slower than 33 mhz. the bt848 data fifo only supports systems where the maximum input data rate is less than the output data rate. it can support a input video clock (17.73 mhz) faster than the pci clock (16 mhz) as long as the video data rate does not exceed the available pci burst rate. fsize1 = 70 ffull1 = 68 fsize2 = 35 ffull2 = 34 fsize3 = 35 ffull3 = 34 fsizet = 140 ffullt = 136
bt848/848a/849a single-chip video capture for pci brook t ree 46 f unctional d escription video and control data fifo l848a_a table 10. table of pci bus access latencies video format resolution mode max bus latency before fifo over?w (us) ntsc 30 fps 640 x 480 rgb32 10 rgb24 13 rgb16/ycrcb 4:2:2 20 ycrcb 4:1:1 27 y8, 8-bit dithered, vbi 41 ntsc 30 fps 320 x 240 rgb32 20 rgb24 27 rgb16/ycrcb 4:2:2 41 ycrcb 4:1:1 55 y8, 8-bit dithered, vbi 83 pal/secam 25 fps 768 x 576 rgb32 8 rgb24 11 rgb16/ycrcb 4:2:2 17 ycrcb 4:1:1 23 y8, 8-bit dithered, vbi 34 pal/secam 25 fps 384 x 288 rgb32 17 rgb24 23 rgb16/ycrcb 4:2:2 34 ycrcb 4:1:1 46 y8, 8-bit dithered, vbi 69 effective rate:ntsc 640 x 480 12.27 (pixels/sec) ntsc 320 x 240 6.14 ntsc 720 x 480 13.50 pal 768 x 576 14.75 pal 384 x 288 7.38 the above ?ures are based on a 33.33 mhz pci bus. max bus latency before fifo over?w (us) = fifo fafull limit (effective rate*number of bytes/pixel)
brook t ree 47 f unctional d escription dma controller l848a_a bt848/848a/849a single-chip video capture for pci dma controller the bt848 incorporates a unique dma controller architecture which gives the capture system great ?xibility in its ability to deliver data to memory. it is archi- tected as a small risc engine which runs on a set of instructions generated and maintained in host system memory by the bt848 device driver software. in this architecture, the dma can dynamically change target memory address from one video line to the next. this enables multiple memory targets to be estab- lished for various components of each video frame. for example, an ntsc video frame contains four discrete components which require separate target memory lo- cations: even ?ld video image data, odd ?ld video image data, line 21 closed captioning data and line 15 teletext data. the bt848 dma can concurrently sup- port a display memory target for the even ?ld image, and three separate system memory targets for the odd ?ld image, line 21 data and line 15 data respectively. the bt848 device driver software creates a risc program which runs the dma controller. the risc program resides in host system memory. through the use of the pci target, the risc program puts its own starting address in a bt848 register and makes it available to the dma controller. the dma controller then requests that the pci initiator fetch an instruction. the risc instructions available are write, skip, sync, and jump. the decoded composite video data is stored in the bt848 fifos and the dma controller presents the data to the pci initiator and requests that the data be output to the target memory. the pci initiator outputs the pixel data on the pci bus after gaining access to the pci bus. it is the responsibility of the dma controller to pre- vent and manage the over?w of the bt848 fifos. this is illustrated in figure 23.
bt848/848a/849a single-chip video capture for pci brook t ree 48 f unctional d escription dma controller l848a_a target memory the bt848s fifo dwords are perfectly aligned to the pci bus, i.e. bit 0 of the fifo dwords lines up with bit ad[0] on the pci bus. thus, video scan line data is aligned to target memory locations, and data path combinational logic between the fifo and the pci bus is not required. the target memory for a given scan line of data is assumed to be linear, incre- menting, and contiguous. for a 1024-pixel scan line a maximum of 4 kb of con- tiguous physical memory is required. each scan line can be stored anywhere in the 32-bit address space. a scan line can be broken into segments with each segment sent to a different target area. an image buffer can be allocated to line fragments anywhere in the physical memory, as the line sequence is arbitrary. figure 23. risc block diagram risc instruction buffer dma address and byte counter fifo data buffer risc program counter address/data decoder risc decoder pci initiator control signals op to pci bus interface pixel data [31:0] risc instructions fifo read signals fifo status bits number of bytes available in fifo fifo output [31:0] from fifo dma controller code address risc program start address
brook t ree 49 f unctional d escription dma controller l848a_a bt848/848a/849a single-chip video capture for pci risc program setup and synchronization there are two independent sets of risc instructions in the host memory, one for the odd ?ld and the other for the even ?ld. the ?st ?ld begins with a synchro- nization instruction (see sync in table 11) indicating packed or planar data from the fifo (status[3:0] = fm1 or fm3), and it ends with a sync instruction in- dicating an even or an odd ?ld to follow (status[3:0] = vre or vro). the sec- ond ?ld begins with a sync instruction and ends with a sync instruction followed by a jump instruction back to the ?st ?ld. the sync instructions al- low the synchronization of the fifo output and the risc program start/end points. the software will set up a pixel data ?w by creating a risc instruction se- quence in the host memory for the odd and even ?lds. the dma controller nor- mally branches through the risc instruction sequence via jump instructions. the risc program sequence only needs to be changed when the parameters of the vid- eo capture/preview mode change, otherwise the dma controller continuously cy- cles through the same program which is set up once for control of an entire frame. risc instructions there exist ?e types of packed mode risc instructions (write, writec, skip, sync, jump) to control the data stored in the fifo. three additional pla- nar mode instructions exist, which replace the simple packed mode write/skip instructions. instruction details are listed in table 11. the dma controller switch- es from packed mode to planar mode or vice versa based on the status codes ?w- ing through the fifos along with the pixel data.
bt848/848a/849a single-chip video capture for pci brook t ree 50 f unctional d escription dma controller l848a_a table 11. risc instructions (1 of 4) instruction opcode dwords description write 0001 2 write packed mode pixels to memory from the fifo beginning at the speci?d target address. dword0: [11:0] byte count [15:12] byte enables [23:16] reset/set risc_status [24] irq [25] reserved [26] eol [27] sol [31:28] opcode dword1: [31:0] 32-bit target address byte address of ?st pixel byte. write123 1001 5 write pixels to memory in planar mode from the fifos beginning at the speci- ?d target addresses. dword0: [11:0] byte count #1 byte transfer count from fifo1 [15:12] byte enables [23:16] reset/set risc_status [24] irq [25] reserved [26] eol [27] sol [31:28] opcode dword1: [11:0] byte count #2 byte transfer count from fifo2 [27:16] byte count #3 byte transfer count from fifo3 dword2: [31:0] 32-bit target address byte address for y data from fifo1 dword3: [31:0] 32-bit target address byte address for cb data from fifo2 dword4: [31:0] 32-bit target address byte address for cr data from fifo3
brook t ree 51 f unctional d escription dma controller l848a_a bt848/848a/849a single-chip video capture for pci write1s23 1011 3 write pixels to memory in planar mode from the fifo1 beginning at the speci- ?d target addresses. skip pixels from fifo2 and fifo3. this instruction is used to achieve the yuv9 and yuv12 color modes, where the chroma compo- nents are sub-sampled. dword0: [11:0] byte count #1 byte transfer count from fifo1 [15:12] byte enables [23:16] reset/set risc_status [24] irq [25] reserved [26] eol [27] sol [31:28] opcode dword1: [11:0] byte count #2 byte skip count from fifo2 [27:16] byte count #3 byte skip count from fifo3 dword2: [31:0] 32-bit target address byte address for y data from fifo1 writec 0101 1 write packed mode pixels to memory from the fifo continuing from the cur- rent target address. dword0: [11:0] byte count [15:12] byte enables [23:16] reset/set risc_status [24] irq [25] reserved [26] eol [27] sol cannot be set [31:28] opcode table 11. risc instructions (2 of 4) instruction opcode dwords description
bt848/848a/849a single-chip video capture for pci brook t ree 52 f unctional d escription dma controller l848a_a skip 0010 1 skip pixels by discarding byte count # of bytes from the fifo. this may start and stop in the middle of a dword. dword0: [11:0] byte count [15:12] reserved [23:16] reset/set risc_status [24] irq [25] reserved [26] eol [27] sol [31:28] opcode skip123 1010 2 skip pixels in planar mode by discarding byte count #1 of bytes from the fifo1 and byte count #2 from fifo2 and fifo3. this may start and stop in the mid- dle of a dword. dword0: [11:0] byte count #1 [15:12] reserved [23:16] reset/set risc_status [24] irq [25] reserved [26] eol [27] sol [31:28] opcode dword1: [11:0] byte count #2 [27:16] byte count #3 table 11. risc instructions (3 of 4) instruction opcode dwords description
brook t ree 53 f unctional d escription dma controller l848a_a bt848/848a/849a single-chip video capture for pci jump 0111 2 jump the risc program counter to the jump address. this allows uncondi- tional branching of the sequencer program. dword0: [15:0] reserved [23:16] reset/set risc_status [24] irq [27:25] reserved [31:28] opcode dword1: [31:0] jump address dword-aligned sync 1000 2 skip all data in fifo until the risc instruction status bits equal to the fifo status bits. dword0: [3:0] status [14:4] reserved [15] resync a value of 1 disables fdsr errors [23:16] reset/set risc_status [24] irq [27:25] reserved [31:28] opcode dword1: [31:0] reserved table 11. risc instructions (4 of 4) instruction opcode dwords description
bt848/848a/849a single-chip video capture for pci brook t ree 54 f unctional d escription dma controller l848a_a each risc instruction consists of 1 to 5 dwords. the 32 bits in the dwords relay information such as the opcode, target address, status codes, synchronization codes, byte count/enables, and start/end of line codes. the sol bit in the write and skip instructions indicate that this particular in- struction is the ?st instruction of the scan line. the eol bit in the write and skip instructions indicate that this particular instruction is the last instruction of the scan line. an eol ?g from the fifo along with the last dword for the scan line coincide with ?ishing the last instruction of the scan line. if the fifo eol condition occurs early, then the current instruction and all instructions leading up to the one that contains the eol ?g are aborted. if there is only one instruction to process the line, both sol and eol bits will be set. write, writec and skip control the processing of active pixel data stored in the fifo. these three instructions alone control the sequence of packed mode data written to target memory on a byte resolution basis. the writec instruction does not supply a target address. instead, it relies on continuing from the current dma pointer contained in the target address counter. this value is updated and kept current even during skip mode or fifo overruns. however, writec cannot be used to begin a new line, i.e. this instruction cannot have the sol bit set. write123, write1s23, and skip123 control the processing of active pixel data stored in the fifos. these three instructions alone control the sequence of planar mode data written to target memory on a byte resolution basis. the write1s23 instruction supports further decimation of chroma on a line basis. for each of these instructions, the same number of bytes will be processed from fifo2 and fifo3. the jump instruction is useful for repeating the same even/odd program for ev- ery frame or switching to a new program when the sequence needs to be changed without interrupting the pixel ?w. the sync instruction is used to synchronize the risc program and the pixel data stream. the dma controller achieves this through the use of the status bits in dword0 of the sync instruction, and by matching them to the four fifo status bits provided along with the pixel data. once the dma controller has matched the status bits between the fifo and the risc instruction, it proceeds with outputting data. prior to establishing synchronization, the dma controller reads and discards the fifo data. opcodes 0000 and 1111 are reserved to detect instruction errors. if these op- codes or the other unused opcodes are detected, an interrupt will be set. the dma controller will stop processing until the risc program is re-enabled. this also ap- plies to sync instructions specifying unused or reserved status codes. detecting risc instruction errors is useful for detecting software errors in programming, or ensuring that the dma controller is following a valid risc sequence. in other words, it ensures that the program counter is not pointing to the wrong location. all unused/reserved bits in the instruction dwords must be set to zero.
brook t ree 55 f unctional d escription dma controller l848a_a bt848/848a/849a single-chip video capture for pci complex clipping it is necessary to be able to clip the video image before it is put onto the pci bus when writing video data directly into on-screen display memory. the bt848 sup- ports complex clipping of the video image for those applications which require the displayed video picture to be occluded by graphics objects such as pull-down menu, overlaying graphics window, etc. typically, a target graphics frame buffer controller cannot provide overlay control for the video pixel data stream when it being provided by a pci bus master peripheral to the graphics pci host interface. the bt848 implements clipping by blocking the video image as it is being put onto the pci bus in the areas where graphics are to be displayed, that is, where graphics objects are ?verlaying?the video image. the bt848 cuts out portions of the video image so that it can ?nlay?or ? around the displayed graphics objects. a clip list is provided through the graphics system directdraw interface (ddi) provider to the bt848 device driver software to indicate the areas of the dis- play where the video image is to be occluded. the bt848 driver software interprets the clip list and generates a risc program that blocks writing of video pixels that are to be occluded. this is illustrated in figure 24. figure 24. example of bt848 performing complex clipping system dram y cr cb write #bytes @ line 0 ... write #b @ l40, skip #b, wr #b @ l40 ... sync vro write123 #b @ y, #b @ cr, #b @ cb ... sync vre jump odd field prog packed rgb even field prog planar 4:2:2 cpu host bridge frame buffer video in a window dialog box graphics controller bt848 pci bus
bt848/848a/849a single-chip video capture for pci brook t ree 56 f unctional d escription dma controller l848a_a executing instructions once the dma controller has achieved synchronization between the fifo and the risc program, it proceeds with executing the risc instructions. the data in the fifo will be aligned with the data bytes expected by the risc instructions. the dma controller reads risc instructions and performs burst writes from the fifo. the dma controller can be programmed to wait for 4, 8, 16, or 32 dwords in the fifo before executing a write instruction. setting this fifo trigger point optimizes the bus ef?iency, by not allowing the dma controller to access the bus every time a dword enters the fifo. however, the fifo trigger point is ignored in the case where the dma controller is near the end of an instruction and the num- ber of dwords left to transfer is less than the number of dwords in the fifo. by allowing the instruction to complete, even if the fifo is below its trigger point, the risc instructions can be ?shed sooner for every scan line. otherwise, the dma controller may have to wait for many scan lines before the required number of dwords are present in the fifo, especially when capturing highly scaled down images. there may be several horizontal lines before another dword en- ters the fifo. the fifo trigger point is ignored by the dma controller during all skip in- structions. in the planar mode, the trigger points for the fifos should be set to the same level, even though the luma data is being stored in the y fifo at least twice as fast the chroma data is being stored in the cr and cb fifos. this ensures that the y fifo will be selected ?st to burst data onto the pci bus. when the initiator is disconnected from the pci bus while in the planar mode, it is essential to regain control of the bus as soon as possible and to deliver any queued dwords. the dma controller will ignore the fifo trigger point as it needs to empty the fifo immediately, otherwise it may not have a chance to empty the rest of the fifos before it has to relinquish the bus. this is not a concern in the packed mode because all three fifos are treated as one large fifo. the dma controller immediately stops burst data writes and risc instruction reads when the pci target detects a parity error while the pci initiator is reading the instruction data. this condition also causes an interrupt. fifo over-run conditions there will be cases where the bt848 pci initiator cannot gain control of the pci bus, and the dma controller is not able to execute the necessary write instruc- tions. instead of writing data to the bus, the dma controller reads data out of the fifo and discards the data. to the fifo, it appears as if the dma controller is out- putting to the bus. this allows the fifo over-runs to be handled gracefully, with minimal loss of data. the bt848 is not required to abort a whole scan during fifo over-runs. the dma controller keeps track of the data to the nearest byte, and is able to deliver the rest of the scan line in the case the fifo over-run condition is cleared. the bt848 dma controller is normally monitoring the fifo full counters (ffull) to determine how full the fifos are. however, before the dma control- ler begins a burst write operation to process a write instruction, it is desirable to
brook t ree 57 f unctional d escription dma controller l848a_a bt848/848a/849a single-chip video capture for pci have some headroom in the fifo to allow for more data to enter, while the pci ini- tiator is waiting for the target to respond. hence, the bt848 monitors the fifo al- most full (fafull) counts. the difference between ffull and fafull provides the necessary headroom to handle target latency. table 12 shows the fifo size and fifo full/almost full counts in units of dwords. prior to the dma controller executing the address phase of a pci write trans- action to process a write instruction, the fifo count value must be below the fafull level. at all other times, the fifos must be maintained below the ffull level. the fifo counters for all three fifos are monitored for full/almost full con- ditions in both planar and packed modes. once the dma controller begins the pci bus transaction, it has committed to a target dma start address. if the fifo over?ws while it is waiting for the target to respond, then the initiator must terminate the transaction just after the target re- sponds. this is due to the fact that the dma controller will have to start discarding the fifo data, since the target pointer and the data are out of sync. this terminat- ing condition will be communicated to the bt848 device driver by setting an inter- rupt bit that indicates interfacing to unreasonably slow targets. if an instruction is exhausted while the fifo is in an over-run condition, the bt848 dma controller will continue discarding the fifo data during the next pre-fetched instruction as well. if the dma controller runs out of risc instruc- tions, the fifo continues to ?l up, and pci bus access is still denied, then the dma controller will continue discarding fifo data for the remainder of that scan line. once the bt848 dma controller detects the eol control bits from the fifo, it will attempt to gain access to the pci bus and resynchronize itself with the risc instruction eol status bits. however, if the dma controller is not successful in getting control of the bus, it will keep track of the number of scan lines discarded out of the fifo and will resynchronize itself with the risc program based on the number of eol control signals detected. the planar mode requires that the dma controller give priority to the y fifo to be emptied ?st. in the case that there is a very long latency in getting access to the pci bus, all three fifos will be almost full when the bus is ?ally granted. while bursting the y data, the crcb data is likely to over?w. attempting to deliv- er data from each fifo to the bus will yield poor bus performance. preference is given to the y fifo to ?ish the burst write operation, and if cr or cb fifos each reach a full condition, then the dma controller will discard their data in parallel to delivering the y data. table 12. fifo full/almost full counts fifo size ffull fafull fifo1 70 68 64 fifo2 35 34 32 fifo3 35 34 32 total 140 136 128
bt848/848a/849a single-chip video capture for pci brook t ree 58 f unctional d escription dma controller l848a_a fifo data stream resynchronization the bt848 dma controller is constantly monitoring whether there is a mismatch between the amount of data expected by the risc instruction and the amount of data being provided by the fifo. the dma controller then corrects for the mis- matches and realigns the risc program and the fifo data stream. for example, if the fifo contains a shorter video line that expected by the risc instruction, the dma controller detects the eol control code from the fifo ear- lier than expected. the dma controller then aborts the rest of the risc instruc- tions until it detects the eol control code from the risc program. if the fifo contains a longer video line than expected by the risc instruction, the dmac will not detect the eol control code from the fifo at the expected time. the dmac will continue reading the fifo data, however it will discard the additional fifo data until it reaches the eol control code from the fifo. similarly, if the fifo provides a smaller number of scan lines per ?ld than ex- pected by the risc program, the end of ?ld control codes from the fifo (vre/vro) will arrive early. the dma controller then aborts all risc instruc- tions until the sync status codes from the risc instruction match the end of ?ld status codes from the fifo. if the fifo provides a larger number of scan lines per ?ld than expected by the risc program, the end of ?ld control codes from the fifo (vre/vro) will not arrive at the expected time. again, the fifo data is read by the dmac and dis- carded until the sync status codes from the risc instruction match the end of ?ld status codes from the fifo. the dma controller manages all of the above error conditions, but the fifo data stream resynchronization interrupt bit will be set as well.
brook t ree 59 l848a_a e lectrical i nterfaces input interface analog signal selection the bt848 contains an on-chip 3:1 mux while the bt848a/849a includes an on-chip 4:1 mux. this mux can be used to switch between three composite sources or two composite sources and one s-video source. in the ?st con?uration, con- nect the inputs of the mux (mux0, mux1 and mux2) to the three composite sources. in the second con?uration, connect two inputs to the composite sources and the other input to the luma component of the s-video connector. in both con- ?urations the output of the mux (muxout) should be connected to the input to the luma a/d (yin) and the input to the sync detection circuitry (syncdet). the bt848a/849a does not require muxout be connected to syncdet. when im- plementing s-video, the input to the chroma a/d (cin) should be connected to the chroma signal of the s-video connector. use of the multiplexer is not a requirement for operation. if digitization of only one video source is required, the source may be connected directly to yin and syncdet. multiplexer considerations the multiplexer is not a break-before-make design. therefore, during the multi- plexer switching time it is possible for the input video signals to be momentarily connected together through the equivalent of 200 w . the multiplexers cannot be switched on a real-time pixel-by-pixel basis. autodetection of ntsc or pal/secam video if the bt848 is con?ured to decode both ntsc and pal/secam, the bt848 can be programmed to automatically detect which format is being input to the chip. autodetection will select the proper clock source for the format detected, (if ntsc is detected, xtal0 is selected; if pal/secam is detected, xtal1 is selected.) the bt848 determines the video source input to the chip by counting the num- ber of lines in a frame. based on the result, the format of the video is determined, and xt0 or xt1 is selected for the clock source. automatic format detection will select the clock source, but it will not program the required registers.
bt848/848a/849a single-chip video capture for pci brook t ree 60 e lectrical i nterfaces input interface l848a_a flash a/d converters the bt848 uses two on-chip ?sh a/d converters to digitize the video signals. yref+, cref+ and yref? cref?are the respective top and bottom of the in- ternal resistor ladders. the input video is always ac-coupled to the decoder. cref?and yref?are connected to analog ground. the voltage levels for yref+ and cref+ are controlled by the gain control circuitry. if the input video momentarily exceeds the corresponding ref+ voltage it is indicated by lof and cof in the status register. a/d clamping an internally generated clamp control signal is used to clamp the inputs of the a/d converter for dc restoration of the video signals. clamping for both the yin and cin analog inputs occurs within the horizontal sync tip. the yin input is always restored to ground while the cin input is always restored to clevel. clevel must be set with an external resistor network so that it is biased to the midpoint be- tween cref?and cref+. external clamping is not required because internal clamping is automatically performed (the bt848a and bt849a do not require that clevel be connected to a resistor network). power-up operation upon power-up, the status of the bt848s registers is indeterminate. the rst sig- nal must be asserted to set the register bits to their default values. the bt848 device defaults to ntsc-m format upon reset. automatic gain controls the refout, cref+ and yref+ pins should be connected together as shown in figure 25. in this con?uration, the bt848 controls the voltage for the top of the reference ladder for each a/d. the automatic gain control adjusts the yref+ and cref+ voltage levels until the back porch of the y video input generates a digital code 0x38 from the a/d. crystal inputs and clock generation the bt848 has two pairs of pins, xt0i/xt0o and xt1i/xt1o, that are used to in- put a clock source. if both ntsc and pal video are being digitized, both clock in- puts must be implemented. the xt0 port is used to decode ntsc video and must be con?ured with a 28.63636 mhz source. the xt1 port is used to decode pal video and must be con?ured with a 35.46895 mhz source. if the bt848 is con?ured to decode either ntsc or pal but not both, then only one clock source must be provided to the chip and it must be connected to the xt0i/xt0o port. if a crystal input is not used, the crystal ampli?rs are internally shut down to save power.
brook t ree 61 e lectrical i nterfaces input interface l848a_a bt848/848a/849a single-chip video capture for pci crystals are speci?d as follows: 28.636363 mhz or 35.468950 mhz third overtone parallel resonant 30 pf load capacitance 50 ppm series resistance 40 w or less the following crystals are recommended for use with the bt848: 1 standard crystal (818) 443-2121 2bak28m636363gle30a 2bak35m468950gle30a 2 mmd (714) 444-1402 a30aa3-28.63636 mhz a30aa3-35.46895 mhz 3 ged (619) 591-4170 pkhc49-28.63636-.030-005-40r, 3rd overtone crystal pkhc49-35.46895-.030-005-40r, 3rd overtone crystal 4 m-tron (800) 762-8800 mp-1 28.63636, 3rd overtone crystal mp-1 35.46895, 3rd overtone crystal 5 monitor (619) 433-4510 mm49x3c3a-28.63636, 3rd overtone crystal mm49x3c3a-35.46895, 3rd overtone crystal 6 cts (815) 786-8411 r3b55a30-28.63636, 3rd overtone crystal r3b55a30-35.46895, 3rd overtone crystal 7fox (813) 693-0099 hc49u-28.63636, 3rd overtone crystal hc49u-35.46895, 3rd overtone crystal the two clock sources may be con?ured with either single-ended oscillators, fundamental cut crystals or third overtone mode crystals, parallel resonant. if sin- gle-ended oscillators are used they must be connected to xt0i and xt1i. the clock source options and circuit requirements are shown in figure 26. the clock source tolerance should be 50 parts-per-million (ppm) or less. devic- es that output cmos voltage levels are required. the load capacitance in the crys- tal con?urations may vary depending on the magnitude of board parasitic capacitance. the bt848 is dynamic, and, to ensure proper operation, the clocks must always be running, with a minimum frequency of 28.636363 mhz.
bt848/848a/849a single-chip video capture for pci brook t ree 62 e lectrical i nterfaces input interface l848a_a figure 25. typical external circuitry mux2 mux3 cin 0.1 m f 1 m w muxout yin syncdet cref yref clevel refout yref+ cref+ vaa 2 k w 0.1 m f 30 k w 30 k w 0.1 m f xt0i xt0o 2.7 m h 22 pf 33 pf 0.1 m f 28.63636 xt1i xt1o 2.2 m h 22 pf 33 pf 0.1 m f 35.46895 0.1 m f jtag i 2 c anti-aliasing filter 75 w termination ac coupling capacitor 1 m w 1 m w mhz mhz analog ground digital ground 0.1 m f vaa vpos agccap vneg 75 w 0.1 m f mux1 75 w 330 pf 330 pf 0.1 m f 3.3 m h mux(0?) 75 w 0.1 m f 75 w 0.1 m f 75 w 0.1 m f optional not required on bt848a/849a not required on bt848a/849a 75 w 0.1 m f mux0 not required on bt848a/849a the mux3 input is only available on the bt848a and bt849a
brook t ree 63 e lectrical i nterfaces input interface l848a_a bt848/848a/849a single-chip video capture for pci figure 26. clock options pal/secam third overtone mode crystal oscillator 2.2 m h 33 pf 0.1 m f 22 pf xt1i xt1o 35.46895 mhz ntsc third overtone mode crystal oscillator 2.7 m h 33 pf 0.1 m f 22 pf xt0i xt0o 28.63636 mhz xt1i xt1o xt0i xt0o 47 pf 47 pf 28.63636 mhz 47 pf 47 pf 35.46895 mhz pal/secam fundamental crystal oscillator ntsc fundamental crystal oscillator 1 m w 1 m w 1 m w 1 m w xt1i xt1o xt0i xt0o pal/secam single-ended oscillator ntsc single-ended oscillator osc osc 28.63636 mhz 35.46895 mhz
bt848/848a/849a single-chip video capture for pci brook t ree 64 e lectrical i nterfaces input interface l848a_a single crystal operation (bt848a/849a only) the bt848a/849a includes an internal phase locked loop that may be used to de- code ntsc and pal using only a single crystal. when using the pll, a 28.636363 mhz, 50 ppm, fundamental (or third overtone) crystal must be con- nected to xt0. this clock is used to generate the clkx2 frequency via the following equation: frequency = (f_input / pll_x) * pll_i.pll_f/pll_c where f_input = 28.63636 mhz (50 ppm) pll_x = reference pre-divider pll_i = integer input pll_f = fractional input pll_c = post divider these values should be programmed as follows to generate pal frequencies: pal (clkx2 = 35.46895 mhz) pll_x = 1 pll_i = 0x0e pll_f = 0xdcf9 pll_c = 0 the pll can be put into low power mode by setting pll_i to zero. for ntsc operation pll_i should be set to zero. in this mode, the correct clock frequency is already input to the system and the pll is shut down. an out of lock or error con- dition is indicated by the plock bit in the pstatus register. when using the pll to generate the required ntsc and pal clock frequencies the following sequence must be followed: initially, tgcki bits in the tgctrl register must be programmed for normal operation of the xtal ports. after the pll registers are programmed, the plock bit in the dstatus register must be polled until it has been veri?d that the pll has attained lock (approximately 500 ms). at that point the tgcki bits are set to select operation via the pll.
brook t ree 65 e lectrical i nterfaces input interface l848a_a bt848/848a/849a single-chip video capture for pci 2x oversampling and input filtering digitized video needs to be bandlimited in order to avoid aliasing artifacts. be- cause the bt848 samples the video data at 8xfsc (over twice the normal rate), no ?tering is required at the input to the a/ds. the analog video needs to be band lim- ited to 14.32 mhz in ntsc and 17.73 mhz in pal/secam mode. normal video signals do not require additional external ?tering. however, if noise or other sig- nal content is expected above these frequencies, the optional anti-aliasing ?ter shown in figure 25 may be included in the input signal path. after digitization, the samples are digitally low pass ?tered and then decimated to 4xfsc. the response of the digital low pass ?ter is shown in figure 27. the digital low pass ?ter pro- vides the digital bandwidth reduction to limit the video to 6 mhz. figure 27. luma and chroma 2x oversampling filter ntsc pal/secam ntsc pal/secam
bt848/848a/849a single-chip video capture for pci brook t ree 66 e lectrical i nterfaces pci bus interface l848a_a pci bus interface the pci local bus is an architectural, timing, electrical, and physical interface that allows the bt848 to interface to the local bus of a host cpu. bt848 is fully com- pliant with pci rev. 2.1 speci?ations. the supported bus cycles for the pci initiator and target are as follows: memory read memory write the supported bus cycles for the pci target only are as follows: con?uration read con?uration write memory read multiple memory read line memory write and invalidate memory write and invalidate is treated in the same manner as memory write. memory read multiple and memory read line are treated in the same manner as memory read. the unsupported pci bus features are as follows: 64-bit bus extension i/o transactions special, interrupt acknowledge, dual address cycles locked transactions caching protocol initiator fast back-to-back transactions to different targets as a pci master, bt848 supports agent parking, ad[31:0], cbe [3:0], and par driven if gnt is asserted and follows an idle cycle (regardless of the state of bus master). all bus commands accepted by the bt848 as a target require a minimum of 3 clock cycles. this allows for a full internal clock cycle address decode time (me- dium devsel timing) and a registered state machine interface. write burst transac- tions can continue with zero wait state performance on the fourth clock cycle and onward (unless writing to video decoder/scaler registers). all read burst transac- tions contain 1 wait-state per data phase. a block diagram of the pci interface is shown in figure 28.
brook t ree 67 e lectrical i nterfaces pci bus interface l848a_a bt848/848a/849a single-chip video capture for pci figure 28. pci block diagram dma controller pci initiator pci target i 2 c master pci con?. registers local registers gpio interrupts pci bus interface fifo data fifo control signals video decoder interrupts int a clk pci control signals
bt848/848a/849a single-chip video capture for pci brook t ree 68 e lectrical i nterfaces general purpose i/o port l848a_a general purpose i/o port the bt848 provides a 24-bit wide general purpose i/o port. there are two modes of operation for the gpio port: normal mode and synchronous pixel interface (spi) mode. in the normal mode, the gpio port is used as a general purpose port enabling 24-bits of data to be input or output (figure 29). in the spi input mode, the gpio port can be used to input the video data from an external video decoder and bypass the bt848s video decoder block (figure 30). in the spi output mode, the output of the bt848s video decoder can be passed over the gpio bus (figure 31), while being utilized by the rest of the bt848 circuitry. in addition to the 24 i/o bits, the gpio port includes an interrupt pin, and a write enable pin. the gpintr signal sets the bit in the interrupt register and caus- es an interrupt condition to occur. the gpwe signal enables sampling of the data on the gpio port and places the data in an internal gpio register. the polarity of the gpwe pin is programmable. the spi output mode is automatically enabled if gpwe is sampled high and gpintr is sampled low upon release of the rst pin. this overrides the gpio- mod bits in the gpio/dma control register and can only be returned to register control by assertion of the rst pin while gpwe and gpintr are in any other states than high and low respectively. care must be taken to ensure the state of gpwe and gpintr are con?ured correctly for the desired use of the gpio pins. internal pullups are provided on both pins. figure 29. gpio normal mode video decoder scaler video data format converter fifo dma controller and pci initiator local registers external circuitry gpio port 24 bits of general i/o figure 30. gpio spi input mode video decoder scaler video data format converter fifo dma controller and pci initiator local registers external video decoder gpio port
brook t ree 69 e lectrical i nterfaces general purpose i/o port l848a_a bt848/848a/849a single-chip video capture for pci gpio normal mode in the gpio normal mode, each of the general purpose i/o pins can be pro- grammed individually. an internal register (gpoe) can be programmed to enable the output buffers of the pins selected as outputs. the contents of the gpdata reg- ister are put on the enabled gpio output pins. in the case where the gpio pins are used as general purpose input pins, the contents of the gpio data register are ig- nored and the signals on the gpio bus pins are read through a separate register. the gpio normal mode allows pci burst transfers by providing a 64-dword contiguous address space. this allows the pci bus to burst 64 dwords without having to resend the address for each dword. the 32-bit pci dword is trun- cated and only the lower 24 bits are output over the gpio port. this in effect pro- vides a high speed output bus interface for non-pci external devices. gpio spi modes in the spi input and output modes, the gpio pins are mapped as shown in table 13. note that the gpio signal names correspond to those of a stand-alone video decoder such as the bt819a or bt829. a separate clock pin (gpclk) is used for the clock signal. in the spi input mode, the gpclk signal is used to input an external clock signal. in the spi output mode, the gpclk signal is used to output the bt848s clkx1 (4*fsc). figure 33 and figure 32 show the basic timing rela- tionships for the spi output mode. in the spi input mode, it is assumed that a video decoder similar to the bt819a or bt829 is connected to the gpio port. the ycrcb 4:2:2 pixel stream follows the ccir recommendation when the range bit in the output format register is set to a logical zero. ccir 601 spec- i?s that nominal video will have y values ranging from 16 to 235, and the cr and cb values will range from 16 to 240. however, excursions outside this range are al- lowed to handle non-standard video. the only mandatory requirement is that 0 and 255 be reserved for timing information. figure 31. gpio spi output mode video decoder scaler video data format converter fifo dma controller and pci initiator local registers external circuitry gpio port bt848 video decoder output
bt848/848a/849a single-chip video capture for pci brook t ree 70 e lectrical i nterfaces general purpose i/o port l848a_a table 13. synchronous pixel interface (spi) gpio signals gpio signal description pin number [23] hreset a 64-clock-long active low pulse. it is output following the rising edge of clkx1. the falling edge of hreset indicates the beginning of a new video line. 82 [22] vreset an active low signal that is at least two lines long (for non-vcr sources, vreset is normally six lines long). it is output following the rising edge of clkx1. the falling edge of vreset indicates the beginning of a new ?ld of video output. the falling edge of vreset lags the falling edge of hreset by two clock cycles at the start of an odd ?ld. at the start of even ?lds, the falling edge of vreset is in the middle of a scan line, horizontal count (hpixel/2)+1, on scan line 263 for ntsc and scan line 313 for pal. 83 [21] hactive an active high signal that indicates the beginning of the active video and is output following the rising edge of clkx1. the hactive ?g is used to indi- cate where nonblanking pixels are present. the start and the end of the hactive signal can be adjusted by programming the hdelay and hac- tive registers. 84 [20] dvalid an active high pixel quali?r that indicates whether or not the associated pixel is valid. dvalid is independent of the hactive and vactive signals. dvalid indicates which pixels are valid. dvalid will toggle high outside of the active window, indicating a valid pixel outside the programmed active region. 85 [19] cbflag an active high pulse that indicates when cb data is being output on the chroma stream. during invalid pixels, cbflag holds the value of the last valid pixel. 86 [18] field when high, indicates that an even ?ld (?ld 2) is being output; when low it indicates that an odd ?ld (?ld 1) is being output. the transition of field is synchronous with the end of active video (i.e. the trailing edge of active). the same information can also be derived by latching the hreset signal with vreset . 87 [17] vactive an active high signal that indicates the beginning of the active video and is output following the rising edge of clkx1. the vactive ?g is used to indi- cate where nonblanking pixels are present. the start and the end of the vac- tive signal can be adjusted by programming the vdelay and vactive registers. 88 [16] vbisel an active high signal that indicates the beginning and end of the vertical blanking interval. the end of vbisel will adjust accordingly when vdelay is changed. 89 [15:8] y[7:0] digital pins for the luminance component of the video data stream. 92?9 [7:0] crcb[7:0] digital pins for the chrominance component of the video data stream 110?17
brook t ree 71 e lectrical i nterfaces general purpose i/o port l848a_a bt848/848a/849a single-chip video capture for pci figure 32. video timing in spi mode notes: (1). hreset precedes vreset by two clock cycles at the beginning of fields 1, 3, 5 and 7 to facilitate external field generation. 2. active pin may be programmed to be composite active or horizontal active. 3. field transitions with the end of horizontal active video de?ed by hdelay and hactive. 2? scan lines hreset vreset hactive field vdelay/2 scan lines b eginning of fields 1, 3, 5, 7 (1) 2? scan lines hreset vreset hactive field vdelay/2 scan lines b eginning of fields 2, 4, 6, 8 vactive vbisel vbisel vactive
bt848/848a/849a single-chip video capture for pci brook t ree 72 e lectrical i nterfaces general purpose i/o port l848a_a digital video in support (bt848a/849a only) this section describes how to use the bt848a/849a with a digital camera. the gpio port can be con?ured to accept general digital data streams. the bt848a/849a contains an sram based state machine that isolates the dig- ital video input events from the internal decoder timing. it allows the digital video input h & v events to synchronize the sequencer and the programmable output events to be positioned where needed to synchronize the decoder. a 20 x 20 sram is used to store h & v count values and signal values for gen- eration of timing events. the sram is programmed once for interfacing to a given digital video input standard. the address for the sram is a 20-bit shift register with reset and advance inputs. the sram is written in sequence, in byte-mode, af- ter a reset. then the sram will function normally in video mode. the addr s/r will be advanced every time the h or v value compares exactly to the hc or vc counters, or reset when the hrst signal output is active and the hc reaches the ? nal h value. these register settings can be found in the control register digital video in support (bt848a/849a only). the digital input port on the bt848a and bt849a provides ?xibility for inter- facing to video standards. software for programming the bt848a/bt849a is in- cluded in the development kit for interfacing to the following standards. table 14 provides the alternate pin de?itions when using the digital video-in mode. figure 33. basic timing relationships for spi mode y[7:0] dvalid active gpclk c b flag c r c b [7:0]
brook t ree 73 e lectrical i nterfaces general purpose i/o port l848a_a bt848/848a/849a single-chip video capture for pci ccir656 this is a 27 mb/s interface in the form of cb, y, cr, y, cb, etc. in this sequence, the word sequence cb, y, cr, refers to co-sited and color-difference samples and the following word, y, corresponds to the next luminance sample. in this interface there are two timing reference codes (sav and eav) that occur at the start and end of active video. these 4-byte codes occur at the outside bound- aries of the active video. a 720 pixels in the active video line corresponds to 1440 samples. 1448 bytes make up a video data block (one line of video with reference codes). the full video line consists of 1716 bytes (in 525 line systems) and 1728 (in 626 line systems). the line is broken into two parts. the ?st is blanking, which con- sists of the front porch, hsync, and back porch, 276 (288 in 635 line systems) bytes from eav through sav. the leading edge of hsync occurs 32 (24 in 625 line sys- tems) bytes after the start of the digital line. the ?ld interval is aligned to this leading edge of hsync. see figure 34 for a diagram on the interface. for a full reference on this stan- dard please refer to the ccir (the international radio consultive committee) standards directly. table 14. pin de?ition of gpio port when using digital video-in mode gpio signal description pin number [23] clkx1 output signals for synchronizing to input video. 82 [22] field 83 [21] vactive 84 [20] vsync 85 [19] hactive 86 [18] hsync 87 [17] composite active 88 [16] composite sync 89 [9] vsync/field input signals for synchronizing to input video. 98 [8] hsync 99 [7:0] data cb, yo, cr, y, ... video data input at gpclk = clkx2 rate. 110?17 figure 34. ccir 656 or bytestream interface to digital input port ccir 656 or clock data[7:0] gpclk gpio[7:0] bt848a/849a 8 bytestream video generator (ex. bt829)
bt848/848a/849a single-chip video capture for pci brook t ree 74 e lectrical i nterfaces general purpose i/o port l848a_a modi?d smpte-125 this interface is the same as ccir 656 but the clock runs at 24.54 mhz, and there are 640 active pixels on a 780 pixel line. this clock rate difference provides simple interface for digital cameras from silicon vision and logitech. bytestream the bt848a and bt849a may also accept data as de?ed in the bytestream video interface standard. this interface is completely de?ed in the bt829 video decoder datasheet. see figure 34 for a diagram on this interface. additional digital inter- faces may be implemented by contacting the rockwell applications group.
brook t ree 75 l848a_a e lectrical i nterfaces i 2 c interface bt848/848a/849a single-chip video capture for pci i 2 c interface the inter-integrated circuit (i 2 c) bus is a two-wire serial interface. serial clock and data lines, scl and sda, are used to transfer data between the bus master and the slave device. the bt848 implements a single master i 2 c system, allowing no other i 2 c mas- ter devices, but many slaves may be in the system. the timing for the bus will be derived from the pci clock which may be 33 mhz or slower. bt848s ?ed divide by 16 divider provides a timing resolution of 0.48 m s. a programmable register de- termines the additional divide ratio to divide the clock down to 100 khz or slower rates. the formula for the i 2 c bit rate is as follows: an i 2 c slave may slow down the data transfer rate even further by inserting wait states. the relationship between scl and sda is decoded to provide both a start and stop condition on the bus. to initiate a transfer on the i 2 c bus, the master must transmit a start pulse to the slave device. this is accomplished by taking the sda line low while the scl line is held high. the master should only generate a start pulse at the beginning of the cycle, or after the transfer of a data byte to or from the slave. to terminate a transfer, the master must take the sda line high while the scl line is held high. the master may issue a stop pulse at any time during an i 2 c cycle. since the i 2 c bus will interpret any transition on the sda line during the high phase of the scl line as a start or stop pulse, care must be taken to ensure that data is stable during the high phase of the clock. this is illustrated in figure 35. bit rate pci clock rate 4 16 i2cdiv 4 + () ------------------------------------------------------- = where: i2cdiv = register bits in the i 2 c data/control register figure 35. the relationship between scl and sda s tart s top sda scl
brook t ree 76 l848a_a bt848/848a/849a single-chip video capture for pci e lectrical i nterfaces i 2 c interface an i 2 c write transaction consists of sending a start signal, 2 or 3 bytes of data (checking for a receiver acknowledge after each byte), and a stop signal. the write data is supplied from a 24-bit register with bytes i2cdb0, i2cdb1, and i2cdb2. this 24-bit register is shifted left to provide data serially, with the msb as the ?st bit. an i 2 c write occurs when the r/w bit in the i2cdb0[0] is set to a logical low. the system driver can select to write 2 or 3 bytes of data by selecting the appropriate value for i2cw3b bit. an i 2 c read transaction consists of sending a start signal, 1 byte of data (checking for a receiver acknowledge), reading 1 data byte from the slave, sending the master nack, and sending the stop signal. the data read is shifted into the i2cdb2 register. an i 2 c read occurs when the r/w bit in the i2cdb0[0] is set to a logical one (figure 36). when the read or write operation is completed, bt848 sends an interrupt over the pci bus to the host controller. the status bit rack will indicate whether the operation completed successfully with the correct number of slave acknowledges. in the case where direct control of the i 2 c bus lines is desired, the bt848 device driver can disable the i 2 c hardware control and can take software control of the scl and sda pins. this is useful in applications where the i 2 c bus is used for gen- eral purpose i/o or if a special type of i 2 c operation (such as multi-mastering) needs to be implemented. for detailed information on the i 2 c bus, refer to ?he i 2 c-bus reference guide,? reprinted by brooktree. figure 36. i 2 c typical protocol diagram chip addr data s a chip addr sub - addr s a a a p data d ata r ead d ata w rite 8 bits f rom b t 848 to s lave f rom s lave to b t 848 na p s = start p = stop a = acknowledge na = non acknowledge
brook t ree 77 e lectrical i nterfaces jtag interface l848a_a bt848/848a/849a single-chip video capture for pci jtag interface need for functional veri?ation as the complexity of imaging chips increases, the need to easily access individual chips for functional veri?ation is becoming vital. the bt848 has incorporated special circuitry that allows it to be accessed in full compliance with standards set by the joint test action group (jtag). conforming to ieee p1149.1 ?tandard test access port and boundary scan architecture,?the bt848 has dedicated pins that are used for testability purposes only. jtag approach to testability jtags approach to testability utilizes boundary scan cells placed at each digital pin and digital interface (a digital interface is the boundary between an analog block and a digital block within the bt848). all cells are interconnected into a boundary scan register that applies or captures test data to be used for functional veri?ation of the integrated circuit. jtag is particularly useful for board testers using functional testing methods. jtag consists of ?e dedicated pins comprising the test access port (tap). these pins are test mode select (tms), test clock (tck), test data input (tdi), test data out (tdo) and test reset (trst ). the trst pin will reset the jtag controller when pulled low at any time. veri?ation of the integrated circuit and its connection to other modules on the printed circuit board can be achieved through these ?e tap pins. with boundary scan cells at each digital interface and pin, the bt848 has the capability to apply and capture the respective logic levels. since all of the digital pins are interconnected as a long shift register, the tap logic has ac- cess and control of all the necessary pins to verify functionality. the tap control- ler can shift in any number of test vectors through the tdi input and apply them to the internal circuitry. the output result is scanned out on the tdo pin and exter- nally checked. while isolating the bt848 from other components on the board, the user has easy access to all bt848 digital pins and digital interfaces through the tap and can perform complete functionality tests without using expensive bed-of-nails testers.
bt848/848a/849a single-chip video capture for pci brook t ree 78 e lectrical i nterfaces jtag interface l848a_a optional device id register the bt848 has the optional device identi?ation register de?ed by the jtag spec- i?ation. this register contains information concerning the revision, actual part number, and manufacturers identi?ation code speci? to brooktree. this register can be accessed through the tap controller via an optional jtag instruction. re- fer to table 15. veri?ation with the tap controller a variety of veri?ation procedures can be performed through the tap controller. with a set of four instructions, the bt848 can verify board connectivity at all digital interfaces and pins. the instructions are accessible by using a state machine stan- dard to all jtag controllers and are: sample/preload, extest, id code, and bypass (see figure 37). refer to the ieee p1149.1 speci?ation for details concerning the instruction register and jtag state machine. brooktree has created a bsdl with the at&t bsd editor. should jtag test- ing be implemented, a disk with an ascii version of the complete bsdl ?e may be obtained by calling 1-800-2bt apps. note: not all pcs drive the pci bus trst pin. in these computers, if the trst pin on the bt848 board is connected to trst on the pci bus (which is not driven) there is a potential that the bt848 may power-up in an unde?ed state. in these designs the trst pin on the bt848 must be grounded (dis- abling jtag). table 15. device identi?ation register version part number manufacturer id xxxx 0000001101010000000110101101 0 0848, 0x0350 0x0d6 4 bits 16 bits 11 bits figure 37. instruction register tdi tdo extest 0 sample/preload 0 id code 0 bypass 1
brook t ree 79 l848a_a pc b oard l ayout c onsiderations the layout should be optimized for lowest noise on the bt848 power and ground lines by shielding the digital inputs/outputs and providing good decoupling. the lead length between groups of power and ground pins should be minimized to re- duce inductive ringing. ground planes the ground plane area should encompass all bt848 ground pins, voltage reference circuitry, power supply bypass circuitry for the bt848, the analog input traces, any input ampli?rs, and all the digital signal traces leading to the bt848. the bt848 has digital grounds (gnd) and analog grounds (agnd and vneg). the layout for the ground plane should be such that the two planes are at the same electrical potential, but they should be isolated from each other in the areas sur- rounding the chip. also, the return path for current should be through the digital plane. see figure 38. figure 38. example ground plane layout bt848 1 121 analog ground digital ground ground return (i.e. pci bus connection) circuit board edge 41 81
bt848/848a/849a single-chip video capture for pci brook t ree 80 pc b oard l ayout c onsiderations power planes l848a_a power planes the power plane area should encompass all bt848 power pins, voltage reference circuitry, power supply bypass circuitry for the bt848, the analog input traces, any input ampli?rs, and all the digital signal traces leading to the bt848. the bt848 has digital power (vdd) and analog power (vaa and vpos). the layout for the power plane should be such that the two planes are at the same elec- trical potential, but they should be isolated from each other in the areas surround- ing the chip. also, the source path for current should be through the digital plane. this is the same layout as shown for the ground plane (figure 38). when using a regulator, circuitry must be included to ensure proper power sequencing. the cir- cuitry shown in figure 39 should help in this regard. supply decoupling the bypass capacitors should be installed with the shortest leads possible, consis- tent with reliable operation, to reduce the lead inductance. these capacitors should also be placed as close as possible to the device. each group of vaa and vdd pins should have a 0.1 m f ceramic bypass capac- itor to ground, located as close as possible to the device. additionally, 10 m f capacitors should be connected between the analog power and ground planes, as well as between the digital power and ground planes. these capacitors are at the same electrical potential, but are physically separate, and pro- vide additional decoupling by being physically close to the bt848 power and ground planes. see figure 40 for additional information about power supply de- coupling. digital signal interconnect the digital signals of the bt848 should be isolated as much as possible from the an- alog signals and other analog circuitry. also, the digital signals should not overlay the analog power plane. any termination resistors for the digital signals should be connected to the dig- ital pcb power and ground planes. analog signal interconnect long lengths of closely-spaced parallel video signals should be avoided to mini- mize crosstalk. ideally, there should be a ground line between the video signal trac- es driving the yin and cin inputs. also, high-speed ttl signals should not be routed close to the analog signals to minimize noise coupling.
brook t ree 81 pc b oard l ayout c onsiderations latch-up avoidance l848a_a bt848/848a/849a single-chip video capture for pci latch-up avoidance latch-up is a failure mechanism inherent to any cmos device. it is triggered by static or impulse voltages on any signal input pin exceeding the voltage on the power pins by more than 0.5 v, or falling below the gnd pins by more than 0.5 v. latch-up can also occur if the voltage on any power pin exceeds the voltage on any other power pin by more than 0.5 v. in some cases, devices with mixed signal interfaces, such as the bt848, can ap- pear more sensitive to latch-up. in reality, this is not the case. however, mixed sig- nal devices tend to interact with peripheral devices such as video monitors or cameras that are referenced to different ground potentials, or apply voltages to the device prior to the time that its power system is stable. this interaction sometimes creates conditions amenable to the onset of latch-up. to maintain a robust design with the bt848, the following precautions should be taken: apply power to the device before or at the same time as the interface cir- cuitry. do not apply voltages below gnd?.5 v, or higher than vaa+0.5 v to any pin on the device. do not use negative supply op-amps or any other negative voltage interface circuitry. all logic inputs should be held low until power to the device has settled to the speci?d tolerance. connect all vdd, vaa and vpos pins together through a low imped- ance plane. connect all gnd, agnd and vneg pins together through a low imped- ance plane. figure 39. optional regulator circuitry i n s ystem p ower vaa,vdd o ut g round gnd s uggested part numbers : r egulator t exas i nstruments m a78 mo5m (+5 v) s ystem p ower (+5 v) (+12 v) d iodes must handle of the bt848 and the peripheral circuitry the current requirements
bt848/848a/849a single-chip video capture for pci brook t ree 82 pc b oard l ayout c onsiderations latch-up avoidance l848a_a figure 40. typical power and ground connection diagram and parts list ground c2 c1 c4 + c5 c3 vio +5v + + c6 analog area vdd, vddg vaa, vpos gnd bt848/848a/849a vddp agnd, vneg pci location description vendor part number c1? (1) 0.1 m f ceramic capacitor erie rpe112z5u104m50v c4? (2) 10 m f tantalum capacitor mallory csr13g106km notes: (1). a 0.1 m f capacitor should be connected between each group of power pins and ground as close to the de- vice as possible, (ceramic chip capacitors are preferred). (2). the 10 m f capacitors should be connected between the analog supply and the analog ground, as well as the digital supply and the digital ground. these should be connected as close to the bt848 as possible. 3. these vendor numbers are listed only as a guide. substitution of devices with similar characteristics will not affect the performance of the bt848.
brook t ree 83 l848a_a c ontrol r egister d efinitions bt848 supports two types of address spaces. the con?uration address space in- cludes the pre-de?ed pci con?uration registers, while the memory address space includes all the local registers used by bt848 to control the remaining por- tions of the device. both the pci con?uration address space and the memory ad- dress space start at memory location 0x00. the pci-based system distinguishes the two address spaces based on the initialization device select, pci address and com- mand signals that are issued during the appropriate software commands. pci con?uration space the pci con?uration space de?es the registers used to interface between the host and the pci local bus. this section de?es the organization of the registers within the 64 byte prede?ed header portion of the con?uration space. figure 41 shows the con?uration space header. for details on the pci bus, refer to the pci local bus speci?ation, revision 2.1 .
bt848/848a/849a single-chip video capture for pci brook t ree 84 c ontrol r egister d efinitions pci con?uration space l848a_a the bt848 is a single-function device, and only supports type 0 con?uration cycles. the con?uration space registers are stored in dwords and de?ed by byte addresses. therefore a register one byte in length can have a bit de?ition other than [7:0] (for example [31:24]), depending on its location in the con?uration space. for a discussion on con?uration cycle addressing, refer to section 3.6.4.1 of the pci local bus speci?ation, revision 2.1 . the con?uration space is accessible at all times even though it is not typically accessed during normal operation. these registers are normally accessed by the power on self test (post) code and by the device driver during initialization time. software will however read the status register during normal operation when a pci bus error occurs and is detected by bt848. the con?uration space is accessed when the initialization device select (id- sel) pin is high, and ad[1:0] = 00, otherwise the cycle is ignored. the con?u- ration register addresses are each offset by 4, since ad[1:0] = 00. bt848 supports burst r/w cycles. write operations to reserved, unimplemented, or read-only registers/bits complete normally with the data discarded. read ac- cesses to reserved or unimplemented registers/bits return a data value equal to ze- ro. figure 41. pci con?uration space header device id vendor id status command class code revision id 0x00 0x04 0x08 0x0c 0x10 0x14 0x18 0x1c 0x20 0x24 0x28 0x2c 0x30 0x34 0x38 0x3c reserved reserved reserved reserved reserved interrupt pin interrupt line 31 16 15 0 base address 0 register reserved reserved reserved latency timer reserved max_lat min_gnt header type 0
brook t ree 85 c ontrol r egister d efinitions pci con?uration space l848a_a bt848/848a/849a single-chip video capture for pci internal addressing of bt848 registers occurs via ad[7:2] and the byte enable bits of the pci bus. the 8-bit byte-address for each of the following register loca- tions is {ad[7:2], 00}. as a single-function device, bt848 ignores bits ad[10:8]. cardbus cis pointer and subsystem id/vendorid registers are not implement- ed in bt848. user-de?able features, bist, cache line size, and expansion rom base address register are also not supported. the following types are used to specify how the bt848 registers are implemented: rox: read only with default value = x rw: read/write. all bits initialized to 0 at rst , unless otherwise stated. rw*: same as rw, but data read may not be same as data written. rr: same as rw, but writing a 1 resets corresponding bit location, writing 0 has no effect.
bt848/848a/849a single-chip video capture for pci brook t ree 86 c ontrol r egister d efinitions pci con?uration registers l848a_a pci con?uration registers vendor and device id register pci con?uration header location 0x00 bits type default name description [31:16] ro 0x0350 0x351 device id (bt848/848a) device id (bt849a) identi?s the particular device or part id code. [15:0] ro 0x109e vendor id (brooktree) identi?s manufacturer of device, assigned by the pci sig.
87 c ontrol r egister d efinitions command and status register l848a_a bt848/848a/849a single-chip video capture for pci command and status register pci con?uration header location 0x04 the command[15:0] register provides control over ability to generate and respond to pci cycles. when a zero is writ- ten to this register, bt848 is logically disconnected from the pci bus except for con?uration cycles. the unused bits in this register are set to a logical zero. the status[31:16] register is used to record status information regarding pci bus related events. bits type default name description [31] rr 0 detected parity error set when a parity error is detected, in the address or data, regard- less of the parity error response control bit. [30] rr 0 signaled system error set when serr is asserted. [29] rr 0 received master abort set when master transaction is terminated with master abort. [28] rr 0 received target abort set when master transaction is terminated with target abort. [27] rr 0 signaled target abort set when target terminates transaction with target abort. this occurs when detecting an address parity error. [26:25] ro 01 address decode time responds with medium devsel timing. [24] rr 0 data parity reported a value of 1 indicates that the bus master asserted perr during a read transaction or observed perr asserted by target when writing data to target. the parity error response bit in the com- mand register must have been enabled. [23] ro 1 fb2b capable target capable of fast back-to-back transactions. [8] rw 0 serr enable a value of 1 enables the serr driver. [6] rw 0 parity error response a value of 1 enables parity error reporting. [2] rw 0 bus master a value of 1 enables bt848 to act as a bus initiator. [1] rw 0 memory space a value of 1 enables response to memory space accesses (target decode to memory mapped registers).
bt848/848a/849a single-chip video capture for pci 88 c ontrol r egister d efinitions revision id and class code register l848a_a revision id and class code register pci con?uration header location 0x08 latency timer register pci con?uration header location 0x0c note that bits [23:16] do return 0x00 indicating bt848 is a single-function device and implements header type 0. base address 0 register pci con?uration header location 0x10 bits type default name description [31:8] ro 0x040000 class code bt848 is a multimedia video device. [7:0] ro 0x0x revision id this register identi?s the device revision. bits type default name description [15:8] rw 0x00 latency timer the number of pci bus clocks for the latency timer used by the bus master. once the latency expires, the master must initiate transaction termination as soon as gnt is removed. bits type default name description [31:12] rw assigned by cpu at boot-up relocatable memory pointer determine the location of the registers in the 32-bit addressable memory space. [11:0] ro 0x008 memory usage speci?ation reserve 4 kb of memory-mapped address space for local regis- ters. address space is prefetchable without side effects.
brook t ree 89 c ontrol r egister d efinitions interrupt line, interrupt pin, min_gnt, max_lat register l848a_a bt848/848a/849a single-chip video capture for pci interrupt line, interrupt pin, min_gnt, max_lat register pci con?uration header location 0x3c min_gnt and max_lat values are dependent on target performance (trdy) and video mode (scale factors and color format). these values were chosen for best case target (0 wait-state) and worst-case video delivery (full-resolution 32-bit rgb). bits type default name description [31:25] ro 0x28 max_lat require bus access every 8.5 m s, at a minimum, in units of 250ns. affects the desired settings for the latency timer value. [24:16] ro 0x10 min_gnt desire a minimum grant burst period of 4 m s to empty data fifo, in units of 250ns. affects the desired settings for the latency timer value. set for 128 dwords, with 0 wait states. [15:8] ro 0x01 interrupt pin bt848 interrupt pin is connected to int a , the only one usable by a single function device. [7:0] rw interrupt line the interrupt line register communicates interrupt line routing information between the post code and the device driver. the post code initializes this register with a value specifying to which input (irq) of the system interrupt controller the bt848 interrupt pin is connected. device drivers can use this value to determine interrupt priority and vector information.
bt848/848a/849a single-chip video capture for pci brook t ree 90 c ontrol r egister d efinitions local registers l848a_a local registers bt848s local registers reside in the 4kb memory addressed space. all of the reg- isters correspond to dwords or a subset thereof. the local registers may be written to or read through the pci bus at any time. internal addressing of the bt848 local registers occurs via ad[11:2] and the byte enable bits of the pci bus. the 8-bit byte-address for each of the following register locations is {ad[11:2], 0x00}. any register may be written or read by any combination of the byte enables. the data to/from the video decoder/scaler registers and vdfc will come from pci byte lane 0 (ad[7:0]) only. if the upper byte lanes are enabled for reading, the data returned is zero. thus each register is separated by a byte address offset of four. all non-used addresses are reserved locations and return an unde?ed value. the scaling function needs to be controlled on a ?ld basis to allow for different size/scaled images for preview and capture applications. all registers that affect scaling, translation, and capture on the input side of the fifo provide for even and odd ?ld values that switch automatically on the internal field signal. note: pins with alternate de?itions on the bt848a/849a are indicated by shading.
brook t ree 91 c ontrol r egister d efinitions device status register l848a_a bt848/848a/849a single-chip video capture for pci device status register memory mapped location 0x000 ?(dstatus) upon reset it is initialized to 0x00. cof is the least signi?ant bit. the cof and lof status bits hold their values until reset to their default values by writing to them. the other six bits do not hold their values, but continually output the status. bits type default name description [7] rw 0 pres video present status. video is determined as not present when an input sync is not detected in 31 consecutive line periods. 0 = video not present. 1 = video present. [6] rw 0 hloc device in h-lock. if hsync is found within 1 clock cycle of the expected position of hsync for 32 consecutive lines, this bit is set to a logical 1. once set, if hsync is not found within 1 clock cycle of the expected position of hsync for 32 consecutive lines, this bit is set to a logical 0. 0 = device not in h-lock. 1 = device in h-lock. [5] rw 0 field field status. this bit re?cts whether an odd or even ?ld is being decoded. 0 = odd ?ld. 1 = even ?ld. [4] rw 0 numl this bit identi?s the number of lines found in the video stream. this bit is used to determine the type of video input to the bt848. thirty-two consecutive ?lds with the same number of lines is required before this status bit will change. 0 = 525 line format (ntsc / pal-m). 1 = 625 line format (pal / secam). [3] rw 0 csel crystal select. this bit identi?s which crystal port is selected. 0 = xtal0 input selected. 1 = xtal1 input selected. [2] rw 0 reserved this bit must be set to zero. plock a logical one indicates the pll is out of lock. once s/w has initial- ized the pll to run at the desired frequency, this bit should be read and cleared until it is no longer set (up to 100 ms). then the clock input mode should be switched from xtal to pll. [1] rw 0 lof luma adc over?w. on power-up, this bit is set to 0. if an adc over?w occurs, the bit is set to a logical 1. it is reset after being written to or a chip reset occurs. [0] rw 0 cof chroma adc over?w. on power-up, this bit is set to 0. if an adc over?w occurs, the bit is set to a logical 1. it is reset after being written to or a chip reset occurs.
bt848/848a/849a single-chip video capture for pci brook t ree 92 c ontrol r egister d efinitions input format register l848a_a input format register memory mapped location 0x004 ?(iform) upon reset it is initialized to 0x58. format(0) is the least signi?ant bit. bits type default name description [7] rw 0 reserved this bit must be set to zero. [6:5] rw 10 muxsel used for software control of video input selection. the bt848 can select between three composite video sources, or two composite and one s-video source. 00 = reserved 01 = select mux2 input to muxout 10 = select mux0 input to muxout 11 = select mux1 input to muxout muxsel 00 = select mux3 input to muxout [4:3] rw 11 xtsel if automatic format detection is required, logical 11 must be loaded. logical 01 and 10 are used if software format selection is desired. 00 = reserved 01 = select xt0 input (only xt0 present) 10 = select xt1 input (both xts present) 11 = auto xt select enabled (both xts present) [2:0] rw 000 format automatic format detection may be enabled or disabled. the numl bit is used to determine the input format when automatic format detection is enabled. 000 = auto format detect enabled 001 = ntsc (m) input format 010 = ntsc w/o pedestal (japan) 011 = pal (b, d, g, h, i) input format 100 = pal (m) input format 101 = pal (n) input format 110 = secam input format 111 = reserved format 111 = pal (n-combination) input format
brook t ree 93 c ontrol r egister d efinitions temporal decimation register l848a_a bt848/848a/849a single-chip video capture for pci temporal decimation register memory mapped location 0x008 ?(tdec) upon reset it is initialized to 0x00. dec_rat(0) is the least signi?ant bit. this register enables temporal decimation by discarding a ?ite number of ?lds or frames from the incoming video. msb cropping register memory mapped location 0x00c ?even field (e_crop) memory mapped location 0x08c ?odd field (o_crop) upon reset it is initialized to 0x12. hactive_msb(0) is the least signi?ant bit. see the vactive, vdelay, hactive and hdelay registers for descriptions on the operation of this register. bits type default name description [7] rw 0 dec_field de?es whether decimation is by ?lds or frames. 0 = decimate frames. 1 = decimate ?lds. [6] rw 0 fldalign this bit aligns the start of decimation with an even or odd ?ld. 0 = start decimation on the odd ?ld (an odd ?ld is the ?st ?ld dropped). 1 = start decimation on the even ?ld (an even ?ld is the ?st ?ld dropped). [5:0] rw 000000 dec_rat dec_rat is the number of ?lds or frames dropped out of 60 (ntsc) or 50 (pal/secam) ?lds or frames. 0x00 value disables decimation (all video frames and ?lds are output). bits type default name description [7:6] rw 00 vdelay_msb (1) the most signi?ant two bits of vertical delay register. [5:4] rw 01 vactive_msb the most signi?ant two bits of vertical active register. [3:2] rw 00 hdelay_msb the most signi?ant two bits of horizontal delay register. [1:0] rw 10 hactive_msb the most signi?ant two bits of horizontal active register. notes: (1). for vdelay_msb the e_crop and o_crop address pointer is flipped. to write to the even field, vdelay_msb bits use the odd field address. to write to the odd field, vdelay_msb bits use the even field address.
bt848/848a/849a single-chip video capture for pci brook t ree 94 c ontrol r egister d efinitions vertical delay register, lower byte l848a_a vertical delay register, lower byte memory mapped location 0x010 ?even field (e_vdelay_lo) memory mapped location 0x090 ?odd field (o_vdelay_lo) upon reset it is initialized to 0x16. vdelay_lo(0) is the least signi?ant bit. this 8-bit register is the lower byte of the 10-bit vdelay register. the two msbs of vdelay are contained in the crop register. vdelay de?es the number of half lines between the trailing edge of vreset and the start of active video. vertical active register, lower byte memory mapped location 0x014 ?even field (e_vactive_lo) memory mapped location 0x094 ?odd field (o_vactive_lo) upon reset it is initialized to 0xe0. vactive_lo(0) is the least signi?ant bit. this 8-bit register is the lower byte of the 10-bit vactive register. the two msbs of vactive are contained in the crop register. vactive de?es the number of lines used in the vertical scaling process. horizontal delay register, lower byte memory mapped location 0x018 ?even field (e_delay_lo) memory mapped location 0x098 ?odd field (o_delay_lo) upon reset it is initialized to 0x78. hdelay_lo(0) is the least signi?ant bit. this 8-bit register is the lower byte of the 10-bit hdelay register. the two msbs of hdelay are contained in the crop register. hdelay de?es the number of scaled pixels between the falling edge of hreset and the start of active video. bits type default name description [7:0] rw 0x16 vdelay_lo the least signi?ant byte of the vertical delay register. bits type default name description [7:0] rw 0xe0 vactive_lo the least signi?ant byte of the vertical active register. bits type default name description [7:0] rw 0x78 hdelay_lo the least signi?ant byte of the horizontal delay register. hactive pixels will be output by the chip starting at the fall of hreset.
brook t ree 95 c ontrol r egister d efinitions horizontal active register, lower byte l848a_a bt848/848a/849a single-chip video capture for pci horizontal active register, lower byte memory mapped location 0x01c ?even field (e_hactive_lo) memory mapped location 0x09c ?odd field (o_hactive_lo) upon reset it is initialized to 0x80. hactive_lo(0) is the least signi?ant bit. hactive de?es the number of hor- izontal active pixels per line output by the bt848. this 8-bit register is the lower byte of the 10-bit hactive register. the two msbs of hactive are contained in the crop register. horizontal scaling register, upper byte memory mapped location 0x020 ?even field (e_hscale_hi) memory mapped location 0x0a0 ?odd field (o_hscale_hi) upon reset it is initialized to 0x02. this 8-bit register is the upper byte of the 16-bit hscale register. horizontal scaling register, lower byte memory mapped location 0x024 ?even field (e_hscale_lo) memory mapped location 0x0a4 ?odd field (o_hscale_lo) upon reset it is initialized to 0xac. this 8-bit register is the lower byte of the 16-bit hscale register. bits type default name description [7:0] rw 0x80 hactive_lo the least signi?ant byte of the horizontal active register. bits type default name description [7:0] rw 0x02 hscale_hi the most signi?ant byte of the horizontal scaling ratio. bits type default name description [7:0] rw 0xac hscale_lo the least signi?ant byte of the horizontal scaling ratio.
bt848/848a/849a single-chip video capture for pci brook t ree 96 c ontrol r egister d efinitions brightness control register l848a_a brightness control register memory mapped location 0x028 ?(bright) upon reset it is initialized to 0x00. bright bits type default name description [7:0] rw 0x00 bright the brightness control involves the addition of a twos complement number to the luma channel. brightness can be adjusted in 255 steps, from ?28 to +127. the resolution of brightness change is one lsb (0.39% with respect to the full luma range). hex value binary value brightness changed by number of lsbs percent of full scale 0x80 1000 0000 ?28 ?0% 0x81 1000 0001 ?27 ?9.6% . . . . . . 0xff 1111 1111 ?1 ?.39% 0x00* 0000 0000* 00 0% 0x01 0000 0001 +01 +0.39% . . . . . . 0x7e 0111 1110 +126 +49.2% 0x7f 0111 1111 +127 +49.6%
brook t ree 97 c ontrol r egister d efinitions miscellaneous control register l848a_a bt848/848a/849a single-chip video capture for pci miscellaneous control register memory mapped location 0x02c ?even field (e_control) memory mapped location 0x0ac ?odd field (o_control) upon reset it is initialized to 0x20. sat_v_msb is the least signi?ant bit. bits type default name description [7] rw 0 lnotch this bit is used to include the luma notch ?ter. for monochrome video, the notch ?ter should not be used. this will output full band- width luminance. 0 = enable the luma notch ?ter 1 = disable the luma notch ?ter [6] rw 0 comp when comp is set to logical one, the luma notch is disabled. when comp is set to logical zero, the c adc is disabled. 0 = composite video 1 = y/c component video [5] rw 1 ldec the luma decimation ?ter is used to reduce the high-frequency component of the luma signal. useful when scaling to cif resolu- tions or lower. 0 = enable luma decimation using selectable h ?ter 1 = disable luma decimation [4] rw 0 cbsense this bit controls whether the ?st pixel of a line is a cb pixel or a cr pixel. for example, if cbsense is low and hdelay is an even number, the ?st active pixel output is a cb pixel. if hdelay is odd, cbsense may be programmed high to produce a cb pixel as the ?st active pixel output. 0 = normal cb, cr order 1 = invert cb, cr order [3] rw 0 reserved this bit should only be written with a logical zero. [2] rw 0 con_msb the most signi?ant bit of the luma gain (contrast) value. [1] rw 0 sat_u_msb the most signi?ant bit of the chroma (u) gain value. [0] rw 0 sat_v_msb the most signi?ant bit of the chroma (v) gain value.
bt848/848a/849a single-chip video capture for pci brook t ree 98 c ontrol r egister d efinitions luma gain register, lower byte l848a_a luma gain register, lower byte memory mapped location 0x030 ?(contrast_lo) upon reset it is initialized to 0xd8. contrast_lo(0) is the least signi?ant bit. contrast the least signi?ant byte of the luma gain (contrast) value. bits type default name description [7:0] rw 0xd8 contrast_lo the con_l_msb bit and the contrast_lo register concate- nate to form the 9-bit contrast register. the value in this regis- ter is multiplied by the luminance value to provide contrast adjustment. decimal value hex value % of original signal 511 0x1ff 236.57% 510 0x1fe 236.13% . . . . . . 217 0x0d9 100.46% 216 0x0d8* 100.00% . . . . . . 128 0x080 59.26% . . . . . . 1 0x001 0.46% 0 0x000 0.00%
brook t ree 99 c ontrol r egister d efinitions chroma (u) gain register, lower byte l848a_a bt848/848a/849a single-chip video capture for pci chroma (u) gain register, lower byte memory mapped location 0x034 ?(sat_u_lo) upon reset it is initialized to 0xfe. sat_u_lo(0) is the least signi?ant bit. sat_u_msb in the control regis- ter, and sat_u_lo concatenate to give a 9-bit register (sat_u). sat_u bits type default name description [7:0] rw 0xfe sat_u_lo this register is used to add a gain adjustment to the u component of the video signal. by adjusting the u and v color components of the video stream by the same incremental value, the saturation is adjusted. decimal value hex value % of original signal 511 0x1ff 201.18% 510 0x1fe 200.79% . . . . . . 255 0x0ff 100.39% 254 0x0fe* 100.00% . . . . . . 128 0x080 50.39% . . . . . . 1 0x001 0.39% 0 0x000 0.00%
bt848/848a/849a single-chip video capture for pci brook t ree 100 c ontrol r egister d efinitions chroma (v) gain register, lower byte l848a_a chroma (v) gain register, lower byte memory mapped location 0x038 ?(sat_v_lo) upon reset it is initialized to 0xb4. sat_v_lo(0) is the least signi?ant bit. sat_v_msb in the control register and sat_v_lo concatenate to give a 9-bit register (sat_v). sat_v bits type default name description [7:0] rw 0xb4 sat_v_lo this register is used to add a gain adjustment to the v component of the video signal. by adjusting the u and v color components of the video stream by the same amount, the saturation is adjusted. decimal value hex value % of original signal 511 0x1ff 283.89% 510 0x1fe 283.33% . . . . . . 181 0x0b5 100.56% 180 0x0b4* 100.00% . . . . . . 128 0x080 71.11% . . . . . . 1 0x001 0.56% 0 0x000 0.00%
brook t ree 101 c ontrol r egister d efinitions hue control register l848a_a bt848/848a/849a single-chip video capture for pci hue control register memory mapped location 0x03c ?(hue) upon reset it is initialized to 0x00. hue(0) is the least signi?ant bit. an asterisk indicates the default option. hue bits type default name description [7:0] rw 0x00 hue hue adjustment involves the addition of a twos complement num- ber to the demodulating subcarrier phase. hue can be adjusted in 256 steps in the range ?0? to +89.3?, in increments of 0.7?. hex value binary value subcarrier reference changed by resulting hue changed by 0x80 1000 0000 ?0? +90? 0x81 1000 0001 ?9.3? +89.3? . . . . . . . . 0xff 1111 1111 ?.7? +0.7? 0x00* 0000 0000* 00? 00? 0x01 0000 0001 +0.7? ?.7? . . . . . . . . 0x7e 0111 1110 +88.6? ?8.6? 0x7f 0111 1111 +89.3? ?9.3?
bt848/848a/849a single-chip video capture for pci brook t ree 102 c ontrol r egister d efinitions sc loop control register l848a_a sc loop control register memory mapped location 0x040 ?even field (e_scloop) memory mapped location 0x0c0 ?odd field (o_scloop) upon reset it is initialized to 0x00. reserved(0) is the least signi?ant bit. bits type default name description [7] rw 0 reserved reserved for future use. must be written with a zero. peak this bit determines if the normal luma low pass ?ters are imple- mented via the hfilt bits or if the peaking ?ters are implemented. 0 = normal luma low pass ?tering 1 = use luma peaking ?ters [6] rw 0 cagc this bit controls the chroma agc function. when enabled, chroma agc will compensate for non-standard chroma levels. the compensation is achieved by multiplying the incoming chroma signal by a value in the range of 0.5 to 2.0. 0 = chroma agc disabled 1 = chroma agc enabled [5] rw 0 ckill this bit determines whether the low color detector and removal cir- cuitry is enabled. 0 = low color detection and removal disabled 1 = low color detection and removal enabled [4:3] rw 00 hfilt these bits control the con?uration of the optional 6-tap horizontal low-pass filter. the auto-format mode determines the appropriate low-pass ?ter based on the horizontal scaling ratio selected. the ldec bit in the control register must be programmed to zero to use these ?ters. 00* = auto format. if auto format is selected when horizontally scaling between full resolution and half resolution, no ?- tering is selected. when scaling between one-half and one-quarter resolution, the cif ?ter is used. when scal- ing between one-quarter and one-eighth resolution, the qcif ?ter is used, and at less than one-eight resolution, the icon ?ter is used. 01 = cif 10 = qcif 11 = icon hfilt if the peak bit is set to logical one, the hfilt bits determine which peaking ?ter is selected. 01 = minimum peaking 10 = medium peaking 11 = maximum peaking [2:0] rw 00 reserved these bits must be set to zero.
brook t ree 103 c ontrol r egister d efinitions output format register l848a_a bt848/848a/849a single-chip video capture for pci output format register memory mapped location 0x048 ?(oform) upon reset it is initialized to 0x00. oform(0) is the least signi?ant bit. bits type default name description [7] rw 0 range luma output range: this bit determines the range for the lumi- nance output on the bt848. the range must be limited when using the control codes as video timing. 0 = normal operation (luma range 16?53, chroma range 2?53). y=16 is black (pedestal). cr, cb=128 is zero color information. 1 = full-range output (luma range 0?55, chroma range 2?53) y=0 is black (pedestal). cr, cb=128 is zero color information. [6:5] rw 00 core luma coring: these bits control the coring value used by the bt848. when coring is active and the total luminance level is below the limit programmed into these bits, the luminance signal is trun- cated to zero. 00 = 0 no coring 01 = 8 10 = 16 11 = 32 [4:0] rw 00000 reserved these bits must be set to zero.
bt848/848a/849a single-chip video capture for pci brook t ree 104 c ontrol r egister d efinitions vertical scaling register, upper byte l848a_a vertical scaling register, upper byte memory mapped location 0x04c ?even field (e_vscale_hi) memory mapped location 0x0cc ?odd field (o_vscale_hi) upon reset it is initialized to 0x60. vertical scaling register, lower byte memory mapped location 0x050 ?even field (e_vscale_lo) memory mapped location 0x0d0 ?odd field (o_vscale_lo) upon reset it is initialized to 0x00. bits type default name description [7] rw 0 ycomb luma comb enable: when enabled, the luma comb ?ter performs a weighted average on 2, 3, 4, or 5 lines of luminance data. the coef?ients used for the average are ?ed and no interpolation is performed. when disabled by a logical zero, ?tering and full verti- cal interpolation is performed based upon the value programmed into the vscale register. 0* = vertical low-pass ?tering and vertical interpolation 1 = vertical low-pass ?tering only [6] rw 1 comb chroma comb enable: this bit determines if the chroma comb is included in the data path. if enabled, a full line store is used to average adjacent lines of color information, reducing cross-color artifacts. 0 = chroma comb disabled 1* = chroma comb enabled [5] rw 1 int interlace: this bit is programmed to indicate if the incoming video is interlaced or non-interlaced. for example, if using the full frame as input for vertical scaling, this bit should be programmed high. if using a single ?ld for vertical scaling, this bit should be pro- grammed low. 0 = non-interlace vs 1* = interlace vs [4:0] rw 00000 vscale_hi vertical scaling ratio: these ?e bits represent the most signi? cant portion of the 13-bit vertical scaling ratio register. bits type default name description [7:0] rw 0x00 vscale_lo vertical scaling ratio: these eight bits represent the least signi? cant byte of the 13-bit vertical scaling ratio register. they are con- catenated with ?e bits in vscale_hi. the following equation should be used to determine the value for this register: vscale = ( 0x10000 ?{ [ ( scaling_ratio ) ?1] * 512 } ) & 0x1fff
brook t ree 105 c ontrol r egister d efinitions test control register l848a_a bt848/848a/849a single-chip video capture for pci test control register memory mapped location 0x054 ?(test) this control register is reserved for putting the part into test mode. write operation to this register may cause unde- termined behavior and should not be attempted. a read cycle from this register returns 0x01, and only a write of 0x01 is permitted. agc delay register memory mapped location 0x060 ?(adelay) upon reset, it is initialized to 0x68. burst delay register memory mapped location 0x064 ?(bdelay) upon reset, it is initialized to 0x5d. bdelay(0) is the least signi?ant bit. bits type default name description [7:0] rw 0x68 adelay agc gate delay for back-porch sampling. the following equation should be used to determine the value for this register: adelay = ( 6.8 m s * 4*fsc) + 7 example for an ntsc input signal: adelay = (6.8 m s x 14.32 mhz) + 7 = 104 (0x68) bits type default name description [7:0] rw 0x5d bdelay the burst gate delay for sub-carrier sampling. the following equa- tion should be used to determine the value for this register: bdelay = ( 6.5 m s * 4*fsc) example for an ntsc input signal: bdelay = (6.5 m s x 14.32 mhz) = 93 (0x5d)
bt848/848a/849a single-chip video capture for pci brook t ree 106 c ontrol r egister d efinitions adc interface register l848a_a adc interface register memory mapped location 0x068 ?(adc) upon reset, it is initialized to 0x82. crush is the least signi?ant bit. bits type default name description [7:6] rw 10 reserved these bits should only be written with logical one and logical zero. [5] rw 0 sync_t this bit de?es the voltage level below which the sync signal can be detected. 0 = analog syncdet threshold high (~125 mv) 1 = analog syncdet threshold low (~75 mv) sync_t this bit is reserved in the bt848a and bt849a and must be set to zero. [4] rw 0 agc_en this bit controls the agc function. if disabled refout is not driven and an external reference voltage must be provided. if enabled, refout is driven to control the a/d reference voltage. 0 = agc enabled 1 = agc disabled [3] rw 0 clk_sleep when this bit is at a logical one, the decoder clock is powered down, but the device registers are still accessible. recovery time is approximately one second to return to capturing video. 0 = normal clock operation 1 = shut down the system clock (power down) [2] rw 0 y_sleep this bit enables putting the luma adc in sleep mode. 0 = normal y adc operation 1 = sleep y adc operation [1] rw 1 c_sleep this bit enables putting the chroma adc in sleep mode. 0 = normal c adc operation 1 = sleep c adc operation [0] rw 0 crush when the crush bit is high (adaptive agc), the gain control mechanism monitors the a/ds for over?w conditions. if an over- ?w is detected, the refout voltage is increased, which increases the input voltage range on the a/ds. 0 = non-adaptive agc 1 = adaptive agc
brook t ree 107 c ontrol r egister d efinitions video timing control l848a_a bt848/848a/849a single-chip video capture for pci video timing control memory mapped location 0x6c ?even field (e_vtc) memory mapped location 0xec ?odd field (o_vtc) upon reset, it is initialized to 0x00. vfilt(0) is the least signi?ant bit. bits type default name description [7] rw 0 hsfmt this bit selects between a single-pixel-wide hreset and the standard 64-clock-wide hreset. 0 = hreset is 64 clkx1 cycles wide 1 = hreset is 1 pixel wide hsfmt 1 = hreset is 32 clkx1 cycles wide [6:2] rw 00000 reserved these bits should only be written with a logical zero. [1:0] rw 00 vfilt these bits control the number of taps in the vertical scaling filter. the number of taps must be chosen in conjunction with the horizontal scale factor to ensure the needed data does not over?w the internal fifo. if the ycomb bit in the vscale_hi register is a logical one, the following settings and equations apply: 00* = 2-tap see note 1. 01 = 3-tap see note 2. 10 = 4-tap see note 3. 11 = 5-tap see note 3. if the ycomb bit in the vscale_hi register is a logical zero, the following settings and equations apply: 00* = 2-tap interpolation only. see note 1. 01 = 2-tap and 2-tap interpolation. see note 2. 10 = 3-tap and 2-tap interpolation. see note 3. 11 = 4-tap and 2-tap interpolation. see note 3. note 1: available at all resolutions. note 2: only available if scaling to less than 385 horizontal active pixels (cif or smaller). note 3: only available if scaling to less than 193 horizontal active pixels (qcif or smaller). 1 2 -- - 1z 1 + () 1 4 -- - 12z 1 z 2 ++ () 1 8 -- - 13z 1 3z 2 z 3 +++ () 1 16 ----- - 14z 1 6z 2 4z 3 z 4 ++++ () 1 2 -- - 1z 1 + () 1 4 -- - 12z 1 z 2 ++ () 1 8 -- - 13z 1 3z 2 z 3 +++ ()
bt848/848a/849a single-chip video capture for pci brook t ree 108 c ontrol r egister d efinitions software reset register l848a_a software reset register memory mapped location 0x07c ?(sreset) this command register can be written at any time. read cycles to this register return an unde?ed value. a data write cycle to this register resets the video decoder and scaler registers of bt848 to the default state. writing any data value into this address resets the device. color format register memory mapped location 0x0d4 ?(color_fmt) bits type default name description [7:4] rw 0000 color_odd odd field color format 0000 = rgb32 0001 = rgb24 0010 = rgb16 0011 = rgb15 0100 = yuy2 4:2:2 0101 = btyuv 4:1:1 0110 = y8 0111 = rgb8 (dithered) 1000 = ycrcb 4:2:2 planar 1001 = ycrcb 4:1:1 planar 1010 = reserved 1011 = reserved 1100 = reserved 1101 = reserved 1110 = raw 8x data 1111 = reserved [3:0] rw 0000 color_even even field color format 0000 = rgb32 0001 = rgb24 0010 = rgb16 0011 = rgb15 0100 = yuy2 4:2:2 0101 = btyuv 4:1:1 0110 = y8 0111 = rgb8 (dithered) 1000 = ycrcb 4:2:2 planar 1001 = ycrcb 4:1:1 planar 1010 = reserved 1011 = reserved 1100 = reserved 1101 = reserved 1110 = raw 8x data 1111 = reserved
brook t ree 109 c ontrol r egister d efinitions color control register l848a_a bt848/848a/849a single-chip video capture for pci color control register memory mapped location 0x0d8 ?(color_ctl) a value of 1 enables byte swapping of data entering the fifo. b3[31:24] swapped with b2[23:16] and b1[15:8] swapped with b0[7:0]. bits type default name description [7] rw 0 ext_frmrate when the gpio port is in spi-16 input mode then this bit supplies ntsc(0)/pal(1) which selects the gamma rom. [6] rw 0 color_bars a value of 1 enables a color bars pattern at the input of the vdfc block. [5] rw 0 rgb_ded a value of 0 enables error diffusion for rgb16/rgb15 modes. a value of 1 disables it. [4] rw 0 gamma a value of 0 enables gamma correction removal. the inverse gamma correction factor of 2.2 or 2.8 is applied and auto-selected by the respective mode ntsc/pal. a value of 1 disables gamma correction removal. [3] rw 0 wswap_odd wordswap odd field. a value of 1 enables word swapping of data entering the fifo. w2[31:16] swapped with w0[15:0] [2] rw 0 wswap_even wordswap even field. a value of 1 enables word swapping of data entering the fifo. w2[31:16] swapped with w0[15:0] [1] rw 0 bswap_odd byteswap odd field. a value of 1 enables byte swapping of data entering the fifo. b3[31:24] swapped with b2[23:16] and b1[15:8] swapped with b0[7:0] [0] rw 0 bswap_even byteswap even field. a value of 1 enables byte swapping of data entering the fifo. b3[31:24] swapped with b2[23:16] and b1[15:8] swapped with b0[7:0]
bt848/848a/849a single-chip video capture for pci brook t ree 110 c ontrol r egister d efinitions capture control l848a_a capture control memory mapped location 0x0dc ?(cap_ctl) vbi packet size memory mapped location 0x0e0 ?(vbi_pack_size) vbi packet size / delay memory mapped location 0x0e4 ?(vbi_pack_del) bits type default name description [7:5] rw 000 reserved these bits should only be written with a logical zero. [4] rw 0 dith_frame 0 = dither matrix applied to consecutive lines in a ?ld. 1 = full frame mode. [3] rw 0 capture_vbi_odd a value of 1 enables vbi data to be captured into the fifo during the odd ?ld. [2] rw 0 capture_vbi_even a value of 1 enables vbi data to be captured into the fifo during the even ?ld. [1] rw 0 capture_odd a value of 1 enables odd capture, allows vdfc to write data to fifos during the odd ?ld. [0] rw 0 capture_even a value of 1 enables even capture, allows vdfc to write data to fifos during the even ?ld. bits type default name description [7:0] rw 0x00 vbi_pkt_lo lower 8 bits for the number of raw data dwords (four 8-bit sam- ples) to capture while in vbi capture mode. bits type default name description [7:2] rw 000000 vbi_hdelay the number of clkx1s to delay from the trailing edge of hreset before starting vbi line capture. [1] rw 0 ext_frame a value of 1 extends the frame output capture region to include the 10 lines prior to the default vactive region. [0] rw 0 vbi_pkt_hi upper bit for the number of raw data dwords (four 8-bit sam- ples) to capture while in vbi capture mode.
brook t ree 111 c ontrol r egister d efinitions pll reference multiplier - pll_f_lo (bt848a/849a only) l848a_a bt848/848a/849a single-chip video capture for pci pll reference multiplier - pll_f_lo (bt848a/849a only) memory mapped location - 0x0f0 upon reset it is initialized to 00 pll reference multiplier - pll_f_hi (bt848a/849a only) memory mapped location - 0x0f4 upon reset it is initialized to 00 integer- pll-xci (bt848a/849a only) memory mapped location - 0x0f8 upon reset it is initialized to 00 field capture counter-(fcap) (bt848a/849a only) memory mapped location - 0x0e8 upon reset it is initialized to 00 bits type default name description [7:0] rw 0x00 pll_f_lo lower byte of pll frequency register. bits type default name description [7:0] rw 0x00 pll_f_hi upper byte of pll frequency register bits type default name description [5:0] rw 000000 pll_i pll_i input. range 6?3. if set to 0x00, then the pll sleeps. [6] rw 0 pll_c pll vco post-divider 0 = use 6 for post-divider 1 = use 4 for post-divider [7] rw 0 pll_x pll ref xtal pre-divider 0 = use 1 for pre-divider 1 = use 2 for pre-divider bits type default name description [7:0] rw (1) 0x00 fcntr counts field transitions when any capture bit is set. notes: (1). any write to this register resets the contents to zero.
bt848/848a/849a single-chip video capture for pci brook t ree 112 c ontrol r egister d efinitions interrupt status l848a_a interrupt status memory mapped location 0x100 ?(int_stat) this register provides status of pending interrupt conditions. to clear the interrupts, read this register, then write the same data back. a 1 in the write data clears the particular register bit. the interrupt /status bits can be polled at any time. bits type default name description [31:28] ro riscs set when risc status set bits are set in the risc instruction. reset when risc status reset bits are set. status only, no inter- rupt. [27] ro risc_en a value of 0 indicates the dma controller is currently disabled. sta- tus only, no interrupt. [26] ro reserved [25] ro rack set when i 2 c operation is completed successfully. otherwise, if the receiver does not acknowledge, then this bit will be reset when i2cdone is set. status only, no interrupt. [24] ro field 0 = odd ?ld, 1 = even ?ld. status only, no interrupt. [23:20] ro 0000 reserved [19] rr 0 scerr set when the dma eol sync counter over?ws. this is a severe error which requires the software to restart the ?ld capture pro- cess. also set when sync codes do not match in the data/instruc- tion streams. [18] rr 0 ocerr set when the dma controller detects a reserved/unused opcode in the instruction sequence, or reserved/unused sync status in a sync instruction. in general, this includes any detected risc instruction error. [17] rr 0 pabort set whenever the initiator receives a master or target abort. [16] rr 0 riperr set when a data parity error is detected (parity error response must be set) while the initiator is reading risc instructions. risc_enable is reset by the target to stop the dma immediately. [15] rr 0 pperr set when a parity error is detected on the pci bus for any of the transactions, r/w, address/data phases, initiator/target, issued/sampled perr regardless of the parity error response bit. all parity errors are serious except for data written to display. [14] rr 0 fdsr fifo data stream resynchronization occurred. the number of pixels, lines, or modes passing through fifo does not match risc program expectations. [13] rr 0 ftrgt set when a pixel data fifo overrun condition results in the master, terminating the transaction due to excessive target latency. [12] rr 0 fbus set when a pixel data fifo overrun condition is being handled by dropping as many dwords as needed, indicating bus access latencies are long.
brook t ree 113 c ontrol r egister d efinitions interrupt status l848a_a bt848/848a/849a single-chip video capture for pci [11] rr 0 risci set when the irq bit in the risc instruction is set. [10] ro 0 reserved [9] rr 0 gpint set upon the programmable edge or level of the gpintr pin. [8] rr 0 i2cdone set when an i 2 c read or write operation has completed. [7:6] ro 0 reserved [5] rr 0 vpres set when the analog video signal input changes from present to absent or vice versa. [4] rr 0 hlock set if the horizontal lock condition changes on incoming video. [3] rr 0 oflow set when an over?w is detected in the luma or chroma adcs. [2] rr 0 hsync set when the analog input begins a new video line, or at the gpio hreset leading edge. [1] rr 0 vsync set when field changes on the analog input or gpio input. [0] rr 0 fmtchg set when a video format change is detected, i.e. the analog input changes from ntsc to pal or vice versa. bits type default name description
bt848/848a/849a single-chip video capture for pci brook t ree 114 c ontrol r egister d efinitions interrupt mask l848a_a interrupt mask memory mapped location 0x104 ?(int_mask) risc program counter memory mapped location 0x120 ?(risc_count) risc program start address memory mapped location 0x114 ?(risc_strt_add) bits type default name description [22:0] rw 0x000000 a value of 1 enables the interrupt bit. the bits correspond to the same bits in the interrupt status register. unmasking a bit may generate an interrupt immediately due to a previously pending condition. the pci int a is level sensitive. it remains asserted until the device driver clears or masks the pending request. [23] rw 0 etbf 0 = normal operation 1 = enable tritoni pci controller compatibility. bits type default name description [31:0] ro risc_pc the current value of the risc program counter. this may be slightly ahead of the current instruction due to pre-fetching instruc- tions into the queue. bits type default name description [31:0] rw 0x00000000 risc_ipc base address for the risc program. standard 32-bit memory space byte address, although the software must dword align by setting the lowest two bits to 00. the dma controller begins exe- cuting pixel instructions at this address when risc_enable is set, i.e. the risc program counter is loaded with this pointer at the rising edge of risc_enable.
brook t ree 115 c ontrol r egister d efinitions gpio and dma control l848a_a bt848/848a/849a single-chip video capture for pci gpio and dma control memory mapped location 0x10c ?(gpio_dma_ctl) bits type default name description [15] rw 0 gpintc a value of 0 selects the direct non-inv/inv input from gpintr to go to the interrupt status register. a value of 1 selects the rising edge detect of the gpinti programmed input. [14] rw 0 gpinti a value of 1 inverts the input from the gpintr pin immediately after the input buffer. [13] rw 0 gpwec a value of 0 enables gpio inputs to be registered upon the rising edge of gpwe. a value of 1 enables gpio inputs to be registered upon the falling edge of gpwe. [12:11] rw 00 gpiomode 00 = normal gpio port. see the gpio section for overriding conditions. 01 = synchronous pixel interface output mode. 10 = synchronous pixel interface input mode. 11 = reserved. [10] rw 0 gpclkmode a value of 1 enables clkx1 to be output on gpclk. a value of 0 disables the output and enables gpclk to supply the internal pixel clock during spi-16 input mode, otherwise this pin is assumed to be inactive. [9:8] rw 00 reserved this bit should only be written with a logical zero. [7:6] rw 00 pltp23 planar mode trigger point for fifo2 and fifo3. 00 = 4 dwords 01 = 8 dwords 10 = 16 dwords 11 = 32 dwords [5:4] rw 00 pltp1 planar mode trigger point for fifo1. 00 = 4 dwords 01 = 8 dwords 10 = 16 dwords 11 = 32 dwords [3:2] rw 00 pktp packed mode fifo trigger point. the number of dwords in the fifos in total before the dma controller begins to burst data onto the pci bus. 00 = 4 dwords 01 = 8 dwords 10 = 16 dwords 11 = 32 dwords [1] rw 0 risc_enable a value of 1 enables the dma controller to process pixel data?w instructions beginning at the risc program start address. [0] rw 0 fifo_enable a value of 1 enables the data fifo, while 0 ?shes or resets it.
bt848/848a/849a single-chip video capture for pci brook t ree 116 c ontrol r egister d efinitions gpio output enable control l848a_a gpio output enable control memory mapped location 0x118 ?(gpio_out_en) gpio registered input control memory mapped location 0x11c ?(gpio_reg_inp) gpio data i/o memory mapped location 0x200?x2ff ?(gpio_data) bits type default name description [23:0] rw 0x000000 gpoe writes to this register provide data to the output buffer enables. a value of 1 enables the driver. bits type default name description [23:0] rw 0x000000 gpie writes to this register provide data to the mux selects on the input buffers. a value of 0 selects the direct input data to be read for gpdata. a value of 1 selects the registered input for gpdata. data on the gpio pins is registered upon the programmable edge of gpwe. bits type default name description [23:0] rw gpdata writes to this register provide data to the output buffers. read data is from the input buffer. data from this register can only be read if output enables are set and gpiomode is set to normal.
brook t ree 117 c ontrol r egister d efinitions i 2 c data/control l848a_a bt848/848a/849a single-chip video capture for pci i 2 c data/control memory mapped location 0x110 the data bytes can be read back after writing if i2cdiv is set to 0 (software drive mode). otherwise, since the register will be in shift mode during i2c circuit mode, the read data will be different from the data written to the register. the data read from the slave will be stable after issuing a read slave transaction and i2cdone is set. bits type default name description [31:24] rw i2cdb0 first byte sent in an i 2 c transaction. typically this will be the base or chip 7-bit address and the r/w bit. [23:16] rw i2cdb1 second byte sent in an i 2 c write transaction, usually a sub-address. [15:8] rw i2cdb2 third byte sent in an i 2 c write transaction, usually the data byte. after a read transaction, this byte register will contain the data read from the slave. [7:4] rw 00000 i2cdiv programmable divider after pci clock/16 for sda/scl bit stream gen- eration. this value must be set to zero for software mode. [3] rw 0 i2csync a value of 1 enables bit-level clock synchronization which allows the slave to insert wait states. [2] rw 0 i2cw3b a value of 0 indicates a write transaction is to consist of sending two bytes i2cdb(0?), while a value of 1 indicates a 3-byte write trans- mission. [1] rw 1 i2cscl a value of 1 releases the scl output, and a 0 forces the scl output low. this bit must be set to a 1 during hardware mode. this override is for direct software control of the bus. reading this bit provides access to the buffered scl input pin. [0] rw 1 i2csda a value of 1 releases the sda output, and a 0 forces the sda output low. this bit must be set to a 1 during hardware mode. this override is for direct software control of the bus. reading this bit provides access to the buffered sda input pin.
bt848/848a/849a single-chip video capture for pci brook t ree 118 c ontrol r egister d efinitions i 2 c data/control l848a_a
brook t ree 119 l848a_a c ontrol r egister d igital v ideo i n s upport (b t 848a/849a o nly ) introduction the registers in this section are only required when using the gpio port to input digital video signal. these registers are included to enable the gpio port to seamlessly connect to digital video cameras. digital video signal interface format memory mapped location 0x0fc ?(dvsif) upon reset, it is initialized to 0x000. bits type default name description [2:0] rw 000 vsfmt 000 = analog 001 = ccir65 010 = bytestream 011 = reserved 100 = external hsync, vsync 101 = external hsync, field 110 = reserved 111 = reserved [4:3] rw svref 00 = hs/vs aligned with cb 01 = hs/vs aligned with y0 10 = hs/vs aligned with cr 11 = hs/vs aligned with y1 5 rw vsif_eso enable sync output for synchronizing video input 1 = syncs are outputs 0 = syncs are inputs 6 rw vsif_bcf enable bypass of chroma ?ters. use when hscale is set to 0. 1 = bypass chroma ?ters 0 = use chroma ?ters 7 rw gpx_en remap gpdata [5:0] inputs from gpio [5:0] to gpx [5:0] 1 = remap outputs 0 = outputs are the same as gpio on the bt848
bt848/848a/849a single-chip video capture for pci brook t ree 120 c ontrol r egister d igital v ideo i n s upport (b t 848a/849a o nly ) timing generator load byte l848a_a timing generator load byte memory mapped location 0x080 ?(tglb) upon reset, it is initialized to 00. timing generator control memory mapped location 0x084 ?(tgctrl) upon reset, it is initialized to 00. bits type default name description [7:0] rw 00 tglb load sram 1 byte at a time, in sequence after a tgc_ar. load the least signi?ant byte ?st. each write to this address causes an automatic advance of the sram byte location. reading from this address only reads the current byte. the tgc_ai bit must be pulsed by s/w in order for the sram byte loca- tion to advance. bits type default name description 0 rw 00 tgc_vm timing generator video mode enable. 0 = read/write mode 1 = enable timing generator/read mode 1 rw gpc_ar timing generator address reset. 2 rw tgc_ai timing generator read address increment -active hi pulse incre- ments the read address. [4:3] rw tgcki decoder input clock select. 00 = normal xtal 0/xtal 1 mode 01 = pll 10 = gpclk (1) 11 = gpclk - inverted (1) [6:5] rw tgcko gpclk output clock select 00 = clkx1 01 = xtal 0 input 10 = pll 11 = pll - inverted 7 reserved must be written with a logical zero. notes: (1). since the entire decoder will be running off the external clock gpclk, when selecting the gpclk is activat- ed, the decoder functionality is subject to a halt condition if the input port is disconnected. a clock detect circuit will allow the decoder to fall back on either the pll or the xtal, whichever is enabled via pll_i. if the pll has been put to sleep, then the decoder will fall back on the xtal0 input. the vpres status condition indicates the status of the clock detect output when in digital video input mode which is monitoring gpclk. note that it is desirable for sw to set up the pll to run at the same frequency as the gpclk input, so if the digital camera is disconnected, then blue-field timing will run properly.
brook t ree 121 c ontrol r egister d igital v ideo i n s upport (b t 848a/849a o nly ) luma gain register, lower byte l848a_a bt848/848a/849a single-chip video capture for pci luma gain register, lower byte memory mapped location 0x030 ?(contrast_lo) this is the alternate de?ition for the contrast_lo register when using the bt848a/849a. upon reset it is initialized to 0xd8 (this must be changed to 0x80 to get standard contrast values when in digital video mode). the contrast register when used in digital video input mode, requires different programming time contrast ad- justments as in analog video decode operation. contrast_lo the least signi?ant byte of the luma gain (contrast) value. note: the bright function has the same register de?ition in the digital sec- tion as in the analog section. however, the bright function does precede the contrast function in the decoder signal processing sequence, therefore any brightness applied is also gained by the contrast set- ting. bits type default name description [7:0] rw 0xd8 contrast_lo the con_l_msb bit and the contrast_lo register concate- nate to form the 9-bit contrast register. the value in this regis- ter is multiplied by the luminance value to provide contrast adjustment. decimal value hex value % of original signal 511 0x1ff 399.22% 510 0x1fe 398.43% . . . . . . 217 0x0d9 169.53% 216 0x0d8 168.75% . . . . . . 128 0x080 100% . . . . . . 1 0x001 0.78% 0 0x000 0.00%
bt848/848a/849a single-chip video capture for pci brook t ree 122 c ontrol r egister d igital v ideo i n s upport (b t 848a/849a o nly ) chroma (v) gain register, lower byte l848a_a chroma (v) gain register, lower byte memory mapped location 0x038 ?(sat_v_lo) this is the alternate de?ition for the sat_v_lo register when using the bt848a/849a. upon reset it is initialized to 0xb4 (this must be changed to 0x80 to get standard chroma (v) gain values when in digital video mode). the sat_v register when used in digital video input mode requires different programming to get the same v gain adjustments as in analog video decode operation. sat_v_lo bits type default name description [7:0] rw 0xb4 sat_v_lo this register is used to add a gain adjustment to the v component of the video signal. by adjusting the u and v color components of the video stream by the same amount, the saturation is adjusted. decimal value hex value % of original signal 511 0x1ff 399.22% 510 0x1fe 398.43% . . . . . . 255 0x0ff 199.22% 254 0x0fe 198.44% . . . . . . 128 0x080 100% . . . . . . 1 0x001 0.78% 0 0x000 0.00%
brook t ree 123 c ontrol r egister d igital v ideo i n s upport (b t 848a/849a o nly ) chroma (u) gain register, lower byte l848a_a bt848/848a/849a single-chip video capture for pci chroma (u) gain register, lower byte memory mapped location 0x034 ?(sat_u_lo) this is the alternate de?ition for the sat_u_lo register when using the bt848a/849a. upon reset it is initialized to 0xfe (this must be changed to 0x80 to get standard chroma (u) gain values when in digital video mode). the sat_u register when used in digital video input mode requires different programming to get the same u gain adjustments as in analog video decode operation. sat_u_lo note: the standard 100% settings are also different for secam vs ntsc or pal. bits type default name description [7:0] rw 0xfe sat_u_lo this register is used to add a gain adjustment to the u component of the video signal. by adjusting the u and v color components of the video stream by the same incremental value, the saturation is adjusted. decimal value hex value % of original signal 511 0x1ff 399.22% 510 0x1fe 398.43% . . . . . . 181 0x0b5 141.41% 180 0x0b4 140.63% . . . . . . 128 0x080 100% . . . . . . 1 0x001 0.78% 0 0x000 0.00%
bt848/848a/849a single-chip video capture for pci brook t ree 124 c ontrol r egister d igital v ideo i n s upport (b t 848a/849a o nly ) hdelay/hscale l848a_a hdelay/hscale hdelay = 128 * (#desiredpixels/#hactive pixels) hscale = 4096 * (#hactivepixels/#desiredpixels ?) this is the alternate usage for the hdelay and hscale registers when using the bt848a/849a. the hscale function has not changed, but there are more #hactivepixels standard input formats to consid- er.since overscan, underscan, or normal scan is a subjective requirement, the formula for horizontal scaling may need to be adjusted for each video input format or standard being implemented. hdelay should be set to 128 (0x80) for most pixel formats when unscaled. however, hdelay may need to be empirically determined for video input formats where the normal 0x80 and scaled derivatives do not correctly com- pensate for horizontal misalignment.
brook t ree 125 l848a_a p arametric i nformation dc electrical parameters table 16. recommended operating conditions parameter symbol min typ max units power supply ?analog v aa, vpos 4.75 5.00 5.25 v power supply ?digital v dd, vddp, vddg 4.75 5.00 5.25 v maximum d |v dd ?v aa | 0.5 v mux0, mux1, mux2, and mux3 input range (ac coupling required) 0.5 1.00 2.00 v yin, cin amplitude range (ac coupling required) 0.5 1.00 2.00 v ambient operating temperature t a 0 +70 ?c table 17. absolute maximum ratings parameter symbol min max units v aa (measured to agnd) v aa , v pos 7.00 v v dd (measured to gnd) v dd, vddp, vddg 7.00 v voltage on any signal pin (1) dgnd ?0.5 v dd + 0.5 v analog input voltage agnd ?0.5 v aa + 0.5 v ambient operating temperature t a 0 +70 ?c storage temperature t s ?5 +150 ?c junction temperature t j +125 ?c vapor phase soldering (15 seconds) t vsol +220 ?c notes: (1). stresses above those listed may cause permanent damage to the device. this is a stress rating only, and functional operation at these or any other conditions above those listed in the operational section of this spec- ification is not implied. exposure to absolute maximum rating conditions for extended periods may affect de- vice reliability. 2. this device employs high-impedance cmos devices on all signal pins. it must be handled as an esd-sen- sitive device. voltage on any signal pin that exceeds the power supply voltage by more than +0.5 v or drops below ground by more than 0.5 v can induce destructive latchup.
bt848/848a/849a single-chip video capture for pci brook t ree 126 p arametric i nformation dc electrical parameters l848a_a table 18. dc characteristics parameter symbol min typ max units digital inputs pci inputs input high voltage (ttl) input low voltage (ttl) gpio/i 2 c input high voltage input low voltage input high voltage (xt0i, xt1i) input low voltage (xt0i, xt1i) input high current (v in =2.7 v) input low current (v in =0.5 v) input capacitance (f=1 mhz, v in =2.4 v) v ih v il v ih v il v ih v il i ih i il c in 2.0 ?.5 2.0 ?.5 3.5 gnd ?0.5 5 v ddp + 0.5 0.8 v ddg + 0.5 0.8 v ddp + 0.5 1.5 70 ?0 v v v v v v m a m a pf digital outputs pci outputs output high voltage (i oh = ? ma) output low voltage (i ol = 6 ma) gpio/i2c output high voltage (i oh = ?00 m a) output low voltage (i ol = 3.2 ma) 3-state current output capacitance v oh v ol v oh v ol i oz c o 2.4 2.4 5 v ddp 0.55 v ddg 0.4 10 v v v v m a pf analog pin input capacitance c a 5pf
brook t ree 127 p arametric i nformation ac electrical parameters l848a_a bt848/848a/849a single-chip video capture for pci ac electrical parameters table 19. clock timing parameters parameter symbol min typ max units ntsc: 8*f sc rate (50 ppm source required) f s2 28.636363 mhz pal: 8*f sc rate (50 ppm source required) f s2 35.468950 mhz xt0 and xt1 inputs: cycle time high time low time 1 2 3 28.2 12 12 ns ns ns figure 42. clock timing diagram xt0i or xt1i 1 2 3 table 20. gpio spi mode timing parameters parameter symbol min typ max units ntsc: 4*f sc rate f s1 14.318181 mhz pal: 4*f sc rate f s1 17.734475 mhz gpclk duty cycle gpclk (falling edge) to data delay data/control setup to gpclk (falling edge) data/control hold to gpclk (falling edge) 4 5 6 45 0 5 5 55 15 % ns ns ns gpclk input: cycle time low time high time 7 8 9 56.4 24 24 ns ns ns figure 43. gpio timing diagram gpclk pixel and gpwe data 4 spi-output pixel and gpwe data spi-input mode 5 6 8 9 7 and digital videoin mode
bt848/848a/849a single-chip video capture for pci brook t ree 128 p arametric i nformation ac electrical parameters l848a_a table 21. power supply current parameters parameter symbol min typ max units supply current v aa =v dd =5.0v, f s2 =28.64 mhz, t=25?c v aa =v dd =5.25v, f s2 =35.47 mhz, t=70?c v aa =v dd =5.25v, f s2 =35.47 mhz, t=0?c supply current, power down i 220 50 262 280 ma ma ma ma table 22. power supply current parameters (bt848a/849a only) supply current v aa =v dd =5.0v, f s2 =28.64 mhz, t=25?c v aa =v dd =5.25v, f s2 =35.47 mhz, t=70?c v aa =v dd =5.25v, f s2 =35.47 mhz, t=0?c supply current, power down i tbd tbd tbd tbd ma ma ma ma table 23. jtag timing parameters parameter symbol min typ max units tms, tdi setup time tms, tdi hold time tck asserted to tdo valid tck asserted to tdo driven tck negated to tdo three-stated tck low time tck high time 10 11 12 13 14 15 16 25 25 10 10 41 11 115 ns ns ns ns ns ns ns figure 44. jtag timing diagram 10 11 15 16 12 13 tdi, tms tck tdo 14
brook t ree 129 p arametric i nformation ac electrical parameters l848a_a bt848/848a/849a single-chip video capture for pci note: test conditions (unless otherwise speci?d): ?ecommended operating conditions. ttl input values are 0? v, with input rise/fall times 3 ns, measured between the 10% and 90% points. timing reference points at 50% for digital inputs and outputs. pixel and control data loads 30 pf and 3 10 pf. gpclk load 50 pf. see pci speci? cation revision 2.1 for pci timing parameters. table 24. decoder performance parameters parameter symbol min typ max units horizontal lock range 7 % of line length fsc, lock-in range 800 hz gain range ? 6 db
bt848/848a/849a single-chip video capture for pci brook t ree 130 p arametric i nformation package mechanical drawing l848a_a package mechanical drawing datasheet revision history figure 45. 160-pin pqfp package mechanical drawing table 25. bt848 datasheet revision history revision date description a 02/07/97 initial release
brooktree division rockwell semiconductor systems, inc. 9868 scranton road san diego, ca 92121-3707 (619) 452-7580 1(800) 2-bt-apps fax: (619) 452-1249 internet: apps@brooktree.com l848a_a brook t ree printed on recycled paper

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